( ESNUG 334 Item 1 ) --------------------------------------------- [10/28/99]
Subject: ( ESNUG 333 #1 ) Verplex, Formality, Anonymity, & "Transit"
> Then, I was introduced to Verplex. Within 2 hours of getting the tool
> installed (and no design center support), I had an RTL to Flat Gates
> comparison completed on the 300k block. Of over 6k key points in the
> block, I had almost all equivalent with the exception of 16 aborted
> points. I then talked to the AEs for Verplex, and had a new release in
> no time that took care of the abort points (interesting to note that the
> aborted points were logic cones in the module that chrysalis could never
> do!). All of this with only 10-15 lines of scripting (definitely not like
> the Chrysalis tool!). I then tried the same block targeted to another
> vendor...BANG! a synopsys bug found with critical state points dropped.
> I have found that Verplex does a great job on RTL2FLATGATES and
> RTL2HIERGATES on blocks <350k. Either 10x performance over the
> competitors or it completes and they don't. Also, the memory usage seems
> to be about 1/2 to 2/3 of the competitors. For post layout, test
> insertion, and ECOs, I can do my 6.5M gate design in less than 1.5 hours.
>
> - [ Big Brother Is Watching ]
From: London Jin <londonj@eng.adaptec.com>
Hi John,
I am very much concerned about thi vague "synthesis bug" Big Brother
mentions in his letter. What kind of scenario is it? Can he please share
with us?
- London Jin
Adaptec
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From: "Alex Koegel" <alexk@smlink.com>
Hi John,
Wait a second,.. 6.5M gates !?? That anon guy [ "Big Brother" ] who posted
must be working for a company that doesn't care about the chip final
production cost.
With a 0.35 um process (7K gates per mm^2), that's a 930 mm^2 -- which is a
30.5mm on-the-side chip.
With a 0.25 um process (15K gates per mm^2), that's a 433 mm^2 -- which is a
20.8mm on-the-side chip. Still huge...
- Alex Koegel
SmartLink - VLSI Group Netantya, Israel
---- ---- ---- ---- ---- ---- ----
From: Jeff Hu <jeff.hu@itexinc.com>
Hi John,
I used to 'delete' ESNUG directly from email list -- not even bother to read
it. That was changed until I found some meat in ESNUG-332. Now I read your
newsletter carefully and try to learn people's experience. However, there
is one thing that I would like to recommend. People who post articles in
ESNUG should include their real name and email address in case readers want
to find out more. There is no need to hide from this user group as long as
the comments he/she made are real.
- Jeff Hu, Cad Manager
ITeX
---- ---- ---- ---- ---- ---- ----
From [ Ground Control To Major Tom ]
Hi, John,
Anon please. I like seeing letters promoting Verplex in ESNUG. They
encourage Synopsys to improve Formality's capacity and speed, and for
Avanti to do the same with Chrysalis.
Verplex is winning yesterday's war by doing only RTL and gate-level
comparisons. They don't discuss it, but Synopsys has transistor-level
equivalence checking in Formality called Transit. It lets you compare
your source RTL with your post-layout transistor netlists (in CDL format.)
- [ Ground Control To Major Tom ]
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