( ESNUG 335 Item 3 ) ---------------------------------------------- [11/3/99]
From: wayne.a.miller@smsc.com ( Wayne Miller )
Subject: Bad Code In Armstrong's "Structured Logic Design with VHDL" Book
Hi John,
I'm in a bind here. I need to be able to explain (with some credibility)
why the following code doesn't work as I would expect it to. I'm
presenting this material to new VHDL users from the text "Structured Logic
Design with VHDL", by Armstrong & Gray. They use lots of non-synthesizable
constructs in their delivery (even their D flip flop example is not
synthesizable!), and I can't explain the following behavior.
This is just one example. It's a simple oscillator, or so I thought.
(Code example converted from BIT types to std_logic.)
library IEEE;
use IEEE.std_logic_1164.all;
entity COSC is
port ( run : in std_logic; clock : out std_logic);
end cosc;
architecture ALG of COSC is
begin
process
begin
wait until RUN='1';
while RUN='1' loop
CLOCK <= '1';
wait for 100 ns;
CLOCK <= '0';
wait for 100 ns;
end loop;
end process;
end ALG;
configuration cfg_cosc of cosc is
for alg
end for;
end cfg_cosc;
Yet when I try it in Synopsys VSS, I get:
%vhdlsim cfg_cosc
# cd cosc
# assign '1' run
# run 200
200 NS
# eval *'signal
RUN '1'
CLOCK 'U'
#
Unless I set RUN to '0' for a few simulation cycles, and then to '1', the
output does not toggle. Why isn't the initial assignment of RUN from 'U'to
'1' considered an event that would trigger "wait until RUN='1';".
I appreciate everybody's help.
- Wayne Miller
Standard Microsystems Corporation Long Island, NY
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