( ESNUG 336 Item 4 ) -------------------------------------------- [11/11/99]
From: [ A Synopsys VCS CAE ]
Subject: Running In 2-State; An Easy Way To Speed Up Your VCS Runs By 50%
Hi John,
I'm a CAE for VCS. I'd like to tell your readers about running VCS in
2-state mode because it can speed up their simulation runs by 50 percent
if it's the right type of Verilog.
In 4-state simulation there are four values for each signal (0,1,X,Z) with
different strengths for each logic level, thus yielding 120 different signal
values. In 2-state simulation, 0 and 1 are the only simulated values, and
the X and Z values in the simulation get mapped to 1 and 0 respectively.
(Obviously this would yield much better simulation performance, since the
simulator has to do much less work per signal.) Turning on the 2-state
option is as simple as adding a "+2state" flag to your VCS command line.
Synthesizable RTL (as opposed to gate-level designs) designs are good
candidates for 2-state simulation. (Many vendors have lots of X's and Z's
in their ASIC libs.) Also, gate-level design are more delay dominated, so
cleaning out X's and Z's probably won't help much.
At the same time some care has to be taken by the user to ensure that X's
and Z's do not affect your simulation's correctness.
VCS does some work to ensure that some strength related constructs such as
pullups, tri, bufif's, etc., maintain their 4-state values. VCS will also
resolve tri-state nets with multiple drivers using a logical "OR". In
addition, it is possible to specify signals that should retain their 4-state
values even while running VCS in 2-state mode. One way to do this is to
embed in your Verilog a directive to keep a signal 4-state no-matter-what.
reg /*4value*/ vec_reg;
(Upcoming versions of VCS will also allow you to specify which modules
should be simulated in 2-state or 4-state.)
Use the compile time switch "+warn2val" to list cases of strength constructs
which may cause simulation mismatch. Some common mismatch issues:
- a frequent sim problem occurs when using a register before it is
initialized through a reset sequence. In 2-state, uninitialized
registers are assigned value 0 (thus creating a negative edge
transition on these registers at time 0). If this negedge transition
is used elsewhere in your design, it could yield a simulation mismatch
that might have not happened using a 4-state simulation. The trick here
is you should initialize all registers using a reset sequence at the
beginning of *any* 2-state simulation run.
- If the Left Hand Side is user specified to be 4-state, the Right Hand
Side must also be 4-state for the Left Hand Side to get the 4-state
values. Example:
reg /*4value*/ vec_reg;
reg ralph;
always @(posedge clk)
vec_reg <= ralph; //RHS is still 2-state !
What I'm saying is that even though you say vec_reg is 4-value, in
a 2-state run, since "ralph" is set to run 2-value, vec_reg will
only take on 2 values. Be aware of this.
- Watch out for casex / casez in your Verilog source. In 2-state, X
is seen as a 1; Z is seen as a 0. Example (assume "selector = 0X") :
reg [1:0] selector;
casex(selector) // assume "selector = 0X"
8'b00: // gets matched in 4-state, but not in 2-state
8'b01: // gets matched in 2-state (4-state also matches,
// but in 4-state the first item is taken)
But let "selector = 0Z"
reg [1:0] selector;
casez(selector) // assume "selector = 0Z"
8'b00: // gets matched in 2-state, but not in 4-state
8'b01: // doesn't get matched in either 2-state nor 4-state
Moral: CAREFULLY watch those casex's and casez's in 2-state mode!
I recommend you make signals like "selector" 4-value to be safe.
- Watch those memory data files containing X and Z values. The values in
the memory data files read in through $readmemh, etc., which have X and
Z values would get mapped to 1 and 0 in 2-state unless the memory is
explicitly tagged as 4-value.
- Plan for 2-state simulation while writing testbenches.
- Never leave control signals at X or Z in 4-state; use a proper reset
sequence at the beginning of any simulation.
- Minimize the number of signals tagged as 4-state in your 2-state
simulation for maximum benefit.
- Use the compile time switch "+warn2val" to report potential issues with
strength resolution.
In summary, many synthesizable RTL designs that don't involve strength
modeling have the potential to simulate much faster in the 2-state mode,
with a few simple changes. You may also want to read the section titled
"Modeling For 2-State Simulation" in the VCS Users Guide.
- [ A Synopsys VCS CAE ]
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