( ESNUG 337 Item 8 ) -------------------------------------------- [11/18/99]
From: "Clifford Cummings" <cliffc@sunburst-design.com>
Subject: Cliff Trashes Navabi's New "Verilog Digital System Design" Book
John -
I know I owe you a review of the book "Logic Synthesis Using Synopsys", a
book that has earned my vote for the Most Flawed Book About Synthesis For
Over $100 -- but in the mean time, you might enjoy another review of a new
Verilog book that I did on behalf of one of my Verilog students. The book:
Zainalabedin Navabi - Verilog Digital System Design - McGraw-Hill, 1999
Four words: "It stinks; run away!"
Most of the acknowledgements in the book are for students, editors and
family. Next time, Mr. Navabi might want some actual Verilog industry
experts to review his text for accuracy and quality. Students only mimic
the professor, editors only make the content pretty, and the family only
shows patience!
It is also common courtesy to correctly spell the names of companies that
provide software to the author. The table of contents lists "F.4 Simulcad
Verilog Software." He did correctly reference the Simucad Silos3 simulator
back in section F.4.
The first two code examples in the book are not Verilog. What's the point?
Figure 1.5 shows the book's first "Verilog description". Unfortunately the
example is not Verilog, it is VHDL!
Indeed, the book appears to be a VHDL book that has been translated to
Verilog (poorly). There is a definite VHDL flavor to the book. Examples:
- The pseudo code description at the top of page 62 uses VHDL
variable assignments.
- The state machine code on page 55 is even a poor coding style
for VHDL.
- Figure 10.16 (page 298) VHDL-like verbose assignments:
ac <= 8'b00000000;
...
mar <= 12'b000000000000;
The more Verilog-like way to make these assignments is:
ac <= 8'h0;
...
mar <= 12'h0;
- The Verilog example in section D.2 (page 423) starts with a
VHDL package.
The first actual Verilog example of the book shows up on page 34. Far too
many silly diagrams and pseudo-code examples occupy the first 33 pages of
the book.
The use of nonblocking assignments in the book is inconsistent and does not
follow common recommendations. Use nonblocking assignments for sequential
logic, use blocking assignments for combinational logic. Example
sequential-code figures that do not use nonblocking assignments include:
- Figure 3.15 (page 36)
- Figure 3.17 (page 38)
- Figures 3.19, 3.27, 3.31, 3.38, 3.44, etc.
- (too many others to enumerate)
Many of the early Verilog examples emphasize Boolean equation and structural
coding styles: Figures 3.19, 3.24, 3.25, 3.38, 3.40. These descriptions are
very low-level and not very synthesis-efficient. The reader is developing
the wrong habits early in the book.
The UDP flip-flop in figure 5.15 on page 97 is wrong. Table entries are
needed to describe what happens on preset and reset transitions. Without
these entries, when reset goes to a 0, the q output will go unknown. Same
problem with the preset signal.
A full Boolean description for a bit comparator in Figure 5.24. Why? If
one is trying to design everything using gate primitives, this might be a
good reference book.
In Figure 6.8 (page 137), using a `include to include a task is pretty
silly. The task cannot be compiled separately (the task code outside of a
module would only produce syntax errors) so there is no point to keep the
task code in a separate file.
In this book, I found very few examples of case statements. I think casez
and casex were only mentioned in one paragraph on page 242. A casez
instruction would have greatly simplified the example in figure 8.9 on
page 188.
The treatment of state machines in section 8.3 is pathetic. Ignore the
coding style shown in this section. The state machine code described at
the top of page 247 and shown in Figures 9.32 and 9.34 includes an initial
block to handle the reset. This is both bad and non-synthesizable.
Initial blocks are not synthesizable and should generally only be used
inside of a testbench.
The first eight chapters are full of gates, instantiations and Boolean
equations. What happened to RTL coding? One might as well do all of the
designs using PLDs and PLD programming languages.
The "Verilog partial code" in Figure 9.41 is not Verilog code. It is a
pseudo description.
More initial blocks in the system_i module in Figure 9.43. Bad.
Non-synthesizable. And again in Figure 9.44. Even initializing signals
in a VHDL model description is a bad idea for synthesis.
RTL coding styles are almost absent from this book.
The Verilog synthesis examples in Appendix E include non-synthesizable
examples. The State machine with initial block on page 441 is one example.
Other examples are inefficiently coded.
Personal opinion -- I find the use of the IEEE-standard schematic symbols
throughout the book to be irritating and distracting.
In case there was any question, I do not recommend this book. In my
opinion, any engineer or engineering student trained using this book
will have to be re-trained before they will become proficient designers
using Verilog.
- Cliff Cummings
Sunburst Design, Inc. Beaverton, OR
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