( ESNUG 337 Item 9 ) -------------------------------------------- [11/18/99]
From: Dieter Peer <peer@iis.fhg.de>
Subject: What Are The Gotchas Concerning Using Behavior Compiler w/ FPGAs?
Hi John, and thanks for running ESNUG forum.
I would like to learn from engineers out there, who use Synopsys Behavior
Compiler (BC) for FPGA design. The problem we permanently run into is that
we target our designs primarily towards ASIC technology, but we would like
to prototype a (set of) FPGA(s), that are functionally identical to the
ASIC, running at full system speed (30 MHz).
The design flow works perfect for "normal" designs (mostly hand-written
VHDL RTL-level code). But we spend far too much time retargeting BC VHDL
code, that perfectly synthesizes for the ASIC, but usually does not fit
while using the same timing constraints with the FPGA design flow.
The question is:
Do other engineers know some "tricks", "general guidelines", or "do's and
dont's" when retargeting Synopsys Behavior Compiler Code to different
technologies?
Perhaps we would not run into these BC problems, if we did *first* target
to the slower (FPGA) technology, and *then* retarget the design to ASIC
technology. But then we might loose performance on the ASIC. Any ideas?
- Dieter Peer
Fraunhofer-Gesellschaft
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