( ESNUG 338 Item 3 ) --------------------------------------------- [12/3/99]
Subject: ( ESNUG 335 #9 ) The Verilog++ Discussion & Co-design's Superlog
> You mentioned a future Verilog++. Well, isn't that what the guys at
> Co-Design are thinking about with their Superlog language? It's a
> definite HW development language, but with some of the features out of
> C/C++. I don't have any experince personally w/ the language. But I've
> listened to the sales pitches of all the companies mentioned in your
> article as well as from Co-Design. Co-Design seems to have thought a
> little bit more closely about HW design issues, such as synthesis, etc.
> Right now you can synthesize Superlog only through a translation into
> Verilog, and I have no idea how that would work quality wise.
>
> - Anna Ekstrandh
> Extreme Packet Devices Inc. Ottawa, Canada
From: David Kelf <davek@co-design.com>
Hi John,
I see in ESNUG all this discussion about using C/C++ as a hardware design
language and thought you might want to see what Superlog looks like.
The Superlog language is based on Verilog but adds a bunch of additional
systems and C like constructs, sort of a Verilog++. So far we are getting
positive feedback from the people we talk to, but are always interested in
other opinions. Here is a chunk of Superlog code to provide a feel of how
it looks:
state {S0, S1, S2} cstate; // state variable with enumeration
always @(posedge reset)
transition (cstate) default: ->> S0; endtransition
always @(posedge clk iff !reset)
transition (cstate)
S0:if (inp == 0) ->>S2; // change state
S2:if (inp == 1) ->> S1; else ->> S0;
S1: ->> S0 n = treeFind("shergar", root);
endtransition
typedef struct {string s; ref node left, right;} node;
ref node n, root; // global data - pointers to nodes
int visited = 0; // global data - number of nodes visited
function ref node treeFind(string str, ref node parent);
if (parent == null) return null;
visited++;
if (str == parent->s) return parent; // string compare
if (str < parent->s) return treeFind(str, parent->left);
else return treeFind(str, parent->right); // recursion
endfunction
This shows how we have brought C and Verilog together, although it's a
little light on some of the interesting systems constructs that are also
present in the language.
Do you have any feedback on the approach we are taking? Do you think your
readers are interested in this approach?
- Dave Kelf, VP Marketingdroid
Co-Design Automation, Inc. Melrose, MA
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