( ESNUG 338 Item 5 ) --------------------------------------------- [12/3/99]
Subject: ( ESNUG 337 #1 ) Customer Q&A On The 1999 Dataquest ASIC Survey
> Our 1999 survey of hardware engineers in the U.S. market for ASIC design
> breaks out as:
>
> 24 % ######################## less than 100 k gates
> 22 % ###################### 100 to 249 k gates
> 4 % #### 250 to 499 k gates
> 16 % ################ 500 to 999 k gates
> 22 % ###################### 1,000 to 2,499 k gates
> 4 % #### 2,500 to 4,999 k gates
> 4 % #### 5,000 to 10,000 k gates
> 2 % ## 10,000 + k gates
>
> Worldwide, there are about 10,000 ASIC design starts.
>
> - Gary Smith, Senior EDA Analyst
> Dataquest San Jose, CA
From: Nick Summerville <nsummerv@ford.com>
To: Gary Smith <gary.smith@gartner.com>
Gary,
What constitutes a gate? When I ask around the industry, I get radically
different answers, from 'a gate is a transistor', to 'a gate is a
placeable standard cell'. Most people (based on what I am told at
conferences) take the number of transistors and divide by either 4 or 6,
and call this the number of gates.
What is your study based on?
- Nick Summerville
Ford Microelectronics Colorado Springs, CO
---- ---- ---- ---- ---- ---- ----
From: Gary Smith <gary.smith@gartner.com>
To: Nick Summerville <nsummerv@ford.com>
Nick,
It's amazing home much of design work is rule of thumb. IMI came up with
the standard CMOS gate in 1974. That was based on four transistors. Now
there are a lot of ways to actually make a gate, but four has stood up as
the rule of thumb. That means you take the number of transistors and
divide by four. These numbers are part of my yearly EDA User Wants & Needs
Report, which is a based on a statistically correct sample of all North
America IC, ASIC, FPGA, PCB, and System Design Engineers. Been doing them
for years now.
- Gary Smith, Senior EDA Analyst
Dataquest San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: Randy Schmidt <rschmidt@us.ibm.com>
To: Gary Smith <gary.smith@gartner.com>
Gary,
What is the typical method used to translate between "movable objects" and
"kgates" for an average ASIC design? How do you account for arrays in
kgates?
- Randy Schmidt
IBM Rochester, MN
---- ---- ---- ---- ---- ---- ----
From: Gary Smith <gary.smith@gartner.com>
To: Randy Schmidt <rschmidt@us.ibm.com>
Randy,
If you mean flip-flops, I always used eight gates as the rule of thumb.
Kgates is a thousand gates so what we're seeing is 2% of the designs are
over 10,000,000 gates. When you translate transistors, when you actually
aren't doing gate level design, into gates I use four transistors per gate.
- Gary Smith, Senior EDA Analyst
Dataquest San Jose, CA
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