( ESNUG 338 Item 6 ) --------------------------------------------- [12/3/99]
Subject: ( ESNUG 335 #2 ) 3-D Load-Dependent Lookup Tables In DC/PT 99.10
> I'd like to rehash an old issue now that it's possible to actually use it.
>
> Synopsys version 1999.10 supports 3-dimensional lookup tables for delay
> modeling. I hope to find out what other tools (e.g., Avanti, Cadence,
> etc.) already have or plan to have compatible timing modeling. What have
> you heard from your vendors? Are there characterization tools out there
> that can write .lib's with this syntax?
>
> Also, the Synopsys docs note that 3D modeling is useful for cells with
> load-dependent outputs, such as unbuffered flops or adders. My local
> Synopsys rep, however, related a customer complaint that even buffered
> outputs exhibit a slight degree of dependence on the other output's
> loading and that the inaccuracies increase with finer geometry processing.
> I'd like to ask the ESNUG readers to please share their experiences with
> this issue and enlighten us.
>
> - Andy Pagones
> Motorola Labs
From: [ The Synopsys Library Compiler CAE ]
Hi John,
I'm the Library Compiler CAE. Since Andy brought this up, I would like to
give a brief history of 3-D timing modeling plus some recommendations.
We've had a lot of experience at Synopsys modeling unbuffered outputs.
In the early days of DC, we modeled one output dependent on output loading
another output, but no output-to-output timing arcs. Many people use this
today, though fewer and fewer libraries heavily leverage unbuffered outputs.
A few years ago we added setup & hold constraint 3-D tables. Some vendors
requested them and 3-D constraint tables are generally used when we have
load dependant constraints. Setup/Hold depends on loads on both Q and Qbar.
During the time when we added 3-D constraint tables, we also added 3-D power
tables for mutually dependent outputs. This was driven by Power tool needs.
Many ASIC vendors use this today. 3-D tables for power should only be used
when one output is complement of other output since table/computation is
based on just one toggle rate.
With DC/PT 99.10 we added 3-D output tables for mutually dependent outputs.
Our main goal was to enable easier SDF back annotation in DC and PrimeTime,
by replacing output-to-output delay arcs, by 3-D input-to-output. SDF has
no notion of output-to-output delay arcs, so there was always some black
magic needed to back-annotate these load dependent arcs in past.
We are aware that even buffered outputs exhibit a slight degree of
dependence on the other output's loading and that the inaccuracies increase
with finer geometry processing. Some ASIC vendors have delay calculation
tools which can handle buffered outputs. Their libraries have characterized
data for 3-D modeling for buffered outputs. (I would welcome customers who
have used such libraries to share their experiences on ESNUG! We don't
recommend modeling buffered output interactions unless effects are fairly
significant. The gate level timing calculation is already an abstractionof
the transistor world. We use the basic assumption of a single toggle case.
This state dependency gives more details but without considering the real
loading/slew on pins outside the signal path!) The 3-D table is
significantly different from the 2-D table using a non-buffered output.
It trades off performance (3-D calculation is more than a degree of
magnitude complex than 2-D) for accuracy. A buffered output might not
justify the cost.
- [ The Synopsys Library Compiler CAE ]
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