( ESNUG 339 Item 7 ) --------------------------------------------- [1/13/00]
From: Dieter Peer <peer@iis.fhg.de>
Subject: ( ESNUG 337 #9 ) Hidden DC/BC Switch To Force Usage Of Xilinx DW
John,
One of my colleagues has found an "undocumented switch" in the DC/BC
software. We now have the following statement in our .synopsys_dc.setup
file:
synlib_preferred_library = {"xdw_virtex"}
This seems to force the compiler to prefer the Xilinx DesignWare (xdw) lib
over the standard DW designware modules, even if the results in the timing
report look worse concerning "design for speed".
As the Xilinx backend place&route (par) tools seem to recognize these xdw
modules in the EDIF netlist, the overal design performance on Virtex-6 is
now about 20% faster. It seems that xdw DesignWare modules are recognized
by Xilinx place&route, thus taking advantage of special interconnect
schemes inside the FPGA.
Unfortunately "xdw_virtex" does not (yet?) contain multipliers, so BC/DC
uses standard designware multipliers, whose Xilinx par routing results look
disadvantageous ("rat's nest style") in the floorplaner, compared to the
clearly structured xdw adder/subtractor blocks.
We are aware of the ESNUG 311 #14 post, that warns of using "hidden,
undocumented features", but in our case it has at least partially improved
our results.
- Dieter Peer
Fraunhofer-Gesellschaft Erlangen, Germany
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