( ESNUG 342 Item 11 ) -------------------------------------------- [2/03/00]
Subject: ( ESNUG 341 #3 ) For Single Paths, Feed DC IPO PrimeTime Verilog
> One of the biggest roadblocks was that we were unable to run DC IPO to
> our satisfaction. It took many days to run (on 360MHz UltraSparcs),
> was repeatably crash-prone, and didn't produce good results. (We tried
> both 98.08-1 "normal" IPO, and 99.05-2 Floorplan Manager IPO). ...
> I wrote a program that reads the Primetime output and upsizes gates
> whose individual delays exceed user-specified limits. That is, it
> looks for and speeds up all the slow gates in the failing paths. ...
>
> - Jeff Winston
> Maker Communications Framingham, MA
From: Denis Bzowy <bzowy@Lucent.COM>
John,
Another way of doing fast DC IPO on a single path is to turn the PrimeTime
timing report into Verilog, e.g.
SBNX3 U94 ( .A( \bff/q[31] ), .Z( n457 )); // .85 pF
MUX21 /maci/U356 ( .SD( n457 ), .Z( /maci/net34253 )); // .41 pF
...
and run this little Verilog with set_load / set_res through Synopsys IPO.
Since IPO considers gate interactions, it gives better results than
gate-at-a-time tools. (Be sure to report_timing before optimizing, too.
For example, you might have A->Z in the path, but a slow transition time
from B->Z .) In theory you could add PDEF for just those gates and run
LBO, but I have not tried this.
For full-chip IPO, we at Lucent Europe have an in-house tool, ZIPO. It's
fast, because it treats gates independently; does no uniquify; uses
Synopsys delay tables; can be told to make modules smaller, or faster,
or fix max_transition; and can add buffers.
- Denis Bzowy
Lucent Microelectronics Munich, Germany
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