( ESNUG 343 Item 10 ) -------------------------------------------- [2/16/00]
Subject: ( ESNUG 342 #13 ) How To Use/Make A .lib Optimal For Synthesis
> We acknowledge if we change Synopsys .lib slightly on its cell repertoire
> or cell timing value, the sythesis result is affected much. When we
> added some new cells, the synthesis result became worse in some cases. We
> changed the cell timing a little bit faster, the result was much improved.
>
> We know that constraints, WLM, cell area and other factors are related
> to determine the synthesis result. But we would like to know if someone
> has a guide line of developing the library: how we should develop library
> optimal for Design Compiler. We tried to find out any application note
> and/or documents on Synopsys SolvNET Web and contacted our Synopsys AE,
> but we can not get useful information so far.
>
> - [ One Of The 47 Ronin ]
From: Nisenbaum Doron <doron@chipx.co.il>
Hi John,
We always had the problems mentioned in this issue (unpredictable synthesis
results per a library change). This is the first time we got some kind of
a guide from the Israel Synopsys support team. It's a 10 page article in
SolvNet titled "DC Library Ultra Guidelines" (October 1999) and it has
the detailed description of the new DC timing model, how to analyze a .lib,
and plus basic library developer guidelines for their new timing model.
It's Synthesis-625.html on SolvNet.
A good, meaty guideline of library developing is sure missing.
- Doron Nisenbaum
Chip Express (Israel) Haifa, Israel
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From: [ Norman de Plume ]
Hi John,
I'm involved in maintaining a 0.35u standard cell library, as well as
providing a backend timing flow.
I'm interested in any discussion on defining what makes a library "synthesis
friendly", how to handle complex timing arcs, synthesis constraints for
place and route, LVS flows for designs with multiple power supplies,
physical verification at 0.25u and below, etc., etc.
I'm looking for insight into defining synthesis constraints. In my past
life, I always relied on the input drive, output loading, and clock
definitions provided by an ASIC vendor. Instead of set_driving_cell, I've
started to use set_input_transition, with a number that was mostly pulled
from the air. How do you derive a number for set_input_transition? Do most
people use a percentage of the clock frequency? Or is it the average
transition of a pad cell loaded by max_fanout NAND gates? Similarly with
max_fanout and output loading, what are reasonable constraints? I know
there will be many points along the banana curve as you sweep max_fanout,
but what determines the "right" number? And finally, should you
set_load = max_fanout * the input cap of a NAND gate
and set_port_fanout_number = max_fanout?
I know these are esoteric questions for most people, but I'd like to start
a discussion for the benefit of all people new to the fine details.
Anon, please.
- [ Norman de Plume ]
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