( ESNUG 344 Item 6 ) --------------------------------------------- [2/23/00]
Subject: ( ESNUG 343 #9 ) Vera & Specman Are A Waste Of User Time & Money
> What are people's experiences with using the Linux version of Vera 4.1.3
> along with VCS 5.1? Do they yield the same results (and performance)
> as their Unix versions? We'll be doing our own evaluation, still it
> would be nice to know ahead of time how successful we'll be.
>
> - Sherri Al-Ashari
> Corvia Networks Sunnyvale, CA
From: Ernst Bernard <Ernst.Bernard@icn.siemens.de>
Hi John,
Sherri may be wasting her time.
I've followed your discussion about testbench environments like Vera and
Specman with much interest. Quite a number of technical details concerning
these tools was provided and other approaches mentioned. Good reading.
There is no question that the approach Vera and Specman pursue has quite a
number of benefits depending on the application. However, testbench
designers would have to undergo the painful process of learning a new
language and mastering new semantics. Having managed this, one can't be
sure of the alleged benefits for a reasonable amount of time. In the
seemingly un-stoppable advent of high-level design and SoC, design
verification methodology will very probably change quite soon causing the
adoption effort not to pay off. Also, the semantics of those proprietary
languages (Vera, Specman, QuickBench) are quite ambiguous w.r.t. timing
compared to well understood HDLs like Verilog or VHDL.
In our ASIC design center we continue therefore to stick to real HDLs (for
us, it's VHDL), though we took a quite close look at Vera and Specman. For
complex chip-level testbenches, we use an in-house VHDL-based environment.
It may lack the convenience of a comfortable GUI but offers a set of very
useful synchronization mechanisms which can't be found in any other
approach. Furthermore, the features of our generators and analyzers can't
be matched by commercial offerings. And I dare to say that in the field of
telecom, directed testing is still more productive than pseudo-random.
Besides this high-level approach, a lot of verification work is done at
block level where the main issue is quickly creating a testbench following
a common methodology. There one doesn't want to bother with the subtleties
of any language, but one wants to create rapidly effective tests. For this
we make use of a tool called BestBench by Diagonal Systems (Switzerland)
which enables a designer to rapidly generate analyzers and generators in a
hierarchical and systematic way but frees him/her from fumbling heavily with
VHDL. The benefits of this tool for block level testbenches are surprising
and we didn't find them in any other tool (e.g. QuickBench).
Both approaches enable the designer to quickly generate powerful testbenches
and allow him to work in his or her usual environment.
I'd be glad to hear in ESNUG from other designers their opinion about
standard versus proprietary testbench languages. We don't think they're
cost effective.
- Ernst Bernard
Siemens AG Munich, Germany
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