( ESNUG 344 Item 13 ) -------------------------------------------- [2/23/00]
From: [ A Synopsys VCS CAE ]
Subject: Overloading Verilog System Tasks (Like $finish & $monitor) In VCS
Hi, John,
I'm a VCS CAE and I thought I'd share one trick of overloading Verilog
system task with your readers.
As you may be aware, the Verilog language has many predefined system tasks;
some of which are non-standard or part of legacy code. Not all simulators
support all such tasks, but in VCS there is an easy way to get rid of such
tasks, or to enhance standard system tasks (like $display, $finish,
$monitor) by overloading them.
Take, for example, $disable_warning. This is a non-standard task (there are
many such tasks like $scope, $showvars, $showscopes, etc.). To run your
design with this task in the design create a .tab (table) file with the
following line:
disable.tab:
==
$disable_warning
==
Then run it by adding -P disable.tab option as follows:
vcs -P disable.tab <other older options>
Have you ever run into a problem with your old testbench where you just
can't figure out which $finish is terminating your simulation? Wouldn't it
be nice if each $finish could output an custom message so that it would be
easier to debug? There is an easy way of doing that just by overloading
the $finish statement in your design where you can see which condition
triggered the $finish (or which $finish amongst the 100's of $finish was
actually executed). Here's how:
finish.v
===
//Comment and uncomment altenatively one of the $finish for this demo
module finish;
lower l1();
//initial #10 $finish;
endmodule
module lower;
initial #10 $finish;
endmodule
Here's where I create my_finish:
finish.c
==
#include <stdio.h>
#include "acc_user.h"
#include "vcsuser.h"
my_finish()
{
s_location s_loc;
p_location loc_p = &s_loc;
handle h1;
h1 = acc_handle_tfinst();
acc_fetch_location(loc_p, h1); /*get the filename and line_no*/
if (! acc_error_flag) /* On success */
io_printf ("Object located in file %s on line %d \n",
loc_p->filename, loc_p->line_no);
tf_dostop(); /* You can do a tf_dofinish also here or
call your own routine */
}
Here's the finish table itself:
finish.tab
==
$finish call=my_finish acc+=r:*
Compile as follows:
vcs -P finish.tab finish.c finish.v -R
The output of above should look something like:
Chronologic VCS simulator copyright 1991-1999
Contains Synopsys proprietary information.
Compiler version 5.1_Beta3; Runtime version 5.1_Beta3; Jan 10 17:19 2000
Object located in file finish.v on line 11
$stop at time 10 Scope: finish.l1 File: finish.v Line: 11
cli_0 >
You can use this type of overloading in many other Verilog system tasks. If
you run into a situation where your simulation testbench outputs too many
$monitor messages, here is an easy way of supressing the same just by
overloading the $monitor system task using VCS .tab file.
Create a monitor.tab file (or add the following line to existing tab file)
with one statement:
monitor.tab
==
$monitor
Then link this file with the rest of your VCS compile options as follows:
vcs -P monitor.tab <rest of the old options>
and run simulation. Those pesky monitor messages are gone. This method is
a bit better than the simv -l simv.log > /dev/null method. This is because
VCS will actually run faster as it doesn't have to do any job when it hits
$monitor.
In summary, use of tab file to overload (or replace) the Verilog system
task is very easy and it's use is limitless.
- [ A Synopsys VCS CAE ]
|
|
