( ESNUG 345 Item 6 ) ---------------------------------------------- [3/1/00]
Subject: ( ESNUG 343 #10 ) Missing: A Meaty DC Library Developer's Guide
> We always had the library problems mentioned (unpredictable synthesis
> results per a library change). This is the first time we got some kind
> of a guide from the Israel Synopsys support team. It's a 10 page article
> in SolvNet titled "DC Library Ultra Guidelines" (October 1999) and it has
> the detailed description of the new DC timing model, how to analyze a
> .lib, and plus basic library developer guidelines for their new timing
> model. It's Synthesis-625.html on SolvNet.
>
> A good, meaty guideline of library developing is sure missing.
>
> - Doron Nisenbaum
> Chip Express (Israel) Haifa, Israel
From: Chris Kiegle <ckiegle@us.ibm.com>
Hi John,
I just wanted to say thanks to Doron Nisenbaum for pointing out the article
on the DC Ultra library guidelines (Synthesis-625.html on SolvNet).
We have been spending a lot of time over the last year or so trying to
examine library structure, content, and the ways that Design Compiler
responds to the library. This task is made even more difficult in creating
a library for use with multiple synthesis tools. We have gotten a lot of
good information from Synopsys about library expectations and library
analysis for Design Compiler. Most of this has come through SVP
connections.
My hope is that Synopsys will provide more information similar to these
library guidelines, make it available to both library developers and chip
designers, and relate it to all the tools. For example, is a library tuned
toward DC Ultra also going to work well with Module Compiler? What are the
constraints that a designer sets that may impact the library analysis & how?
Perhaps an intermediate step could be added to synthesis to spit out the
results of the library analysis and to report the set of cells the synthesis
is initially targeting? That information would be helpful to both library
developers and chip designers to help steer synthesis and make more educated
choices for constraints that impact the initial mapping (and possibly the
implementation selection), like wire load models & set_prefer.
- Chris Kiegle
IBM Microelectronics Burlington, VT
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