( ESNUG 346 Item 11 ) -------------------------------------------- [3/16/00]
Subject: ModelSim's Tcl/Tk vs. Cadence/Synopsys/Exemplar's Tcl Interfaces
> Has anyone experience using tcl/tk with ModelSim? What is the interest
> of using tcl/tk with this tool?
>
> - "Jeff" France
From: Volker Hetzer <volker.hetzer@abg1.siemens.de>
So far I've only seen Tcl/Tk with Cadence Affirma and Synopsys Design
Compiler. There, the benefit was that you've got a whole language to do
scripts in, including socket communication, procedures, file i/o and such.
However, my experience with Synopsys was that it's possible to create a
really messy, ugly Tcl-interface if one tries hard enough. The guys at
Synopsys certainly did.
What Tcl version does your version of ModelSim use? Try "info patchlevel"
to find out. Does it, perchance, offer Tk too? If yes, you've got a real
winner because then you can't do your own graphical interface to ModelSim.
- Volker Hetzer
Siemens Germany
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From: Evan Lavelle <eml@riverside-machines.com>
Tcl seems to be everywhere now - Modelsim's on 8.0 and on Exemplar's
Spectrum rev. 7.6p2. You can modify the GUI on Modelsim - don't know
about Exemplar Spectrum.
- Evan Lavelle
Riverside Machines, Ltd. UK
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From: mark.luscombe@lineone.net (Mark Luscombe)
I have been using Modelsim for a while now, and am starting to do some
larger and more complex simulation runs. Previously, I have just used a
linear sim.do file for providing input data patterns. Now I wanted a more
sophisticated test pattern, and wrote a nested set of sim.do files with
passed arguments using TCL for loops and bit manipulation etc. This works
really well. I was wondering what other designers opinions are concerning
test benches implemented like this with TCL scripts, and ones that use VHDL
with it's file IO capabilities.
- Mark Luscombe
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From: Richard Guerin <guerin@IEEE.org>
IMHO, testbenches are much more powerful and offer more flexibility. For
instance, you can include bus functional models (i.e. CPU, SRAM, Flash,
UART ....) to help test external interfaces, use assertions statements
to help automate testing, instantiate multiple versions of the design
(like RTL and Post-Route) and perform regression testing against outputs,
use TEXTIO packages to read in test vectors from ASCII file (can also write
out test results to ASCII file), etc.
Personally, I'll use a script file for simple design entities or modules.
I'll use a testbench for top level design or any entity that includes
complex interfaces, timing, or protocols. I've found that the extra time
required to generate and debug a test bench is worth it as it can save you
much more time down the road during system level checkout/integration.
- Richard Guerin
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From: Ed Hepler <elh@vu-vlsi.ee.vill.edu>
I have used both Tcl based testbenches and VHDL based testbenches with
ModelSim. It has been a few months since I last used a Tcl testbench.
Note that there is a limit of 9 ($1 - $9) arguments from the command
line when passing arguments to a Tcl function via a "do".
I have also noticed a significant speed improvement when using a
VHDL-based testbench.
- Ed Hepler
Villanova University
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