( ESNUG 348 Item 4 ) --------------------------------------------- [3/30/00]
From: [ Gotta Be Anon ]
Subject: We Compared Mentor's MBistArchitect To LogicVision's memBIST-IC
Hi John,
Please keep me anonymous.
We're looking to purchase a memory BIST tool and have evaluated Mentor's
MBistArchitect and LogicVision's memBIST-IC. Both tools were able to
generated BIST circuitry for a complex asynchronous SRAM macro, so I'm
looking for ESNUG feedback on either tool to aid in our decision.
Here are some of our findings:
1. Both tools allow one controller to test multiple RAMS. Both support
asynchronous and synchronous SRAM, and ROM.
2. MBistArchistect (MBA) was extremely simple to use. As with both tools,
setting up the memory model was the most difficult part.
memBIST-IC (MBIC) was more difficult to set up because it needs to
parse and modify user Verilog.
3. MBIC inserts the mbist into the netlist. This has both positive and
negative implications. Positive: Verilog porting does not need to be
fixed through the hierarchy (the BIST adds several new ports).
Negative: the "golden" RTL code must be frozen and the mbist inserted
to generated the "operating" RTL code for simulation and layout.
With MBA, the engineer has to insert the the mbist manually, but he
controls the final (and single) netlist.
4. Both tools generate a testbench to verify the BISTed memory, at the
memory instance level.
5. MBIC can propogate the testbench to the top level, so mbist tests can
be simulated at the chip level, like they would be on a tester. This
is a manual operation with MBA. Positive: Ease of use. Negative: if
the test procedure is complex (mbist tests are based on register
addresses, etc.), MBIC may not be able to handle this.
6. MBIC can handle parallel or serial mbist with the number of comparators
specified by the user. MBA can only handle full parallel mbist.
7. Both MBA and MBIC can handle reduced data paths for mbist checking:
MBA - compressor (LSFR with signature?)
MBIC - LSFR with signature
8. MBIC provides a report on tester cycles and tester time (based on a
reference clock). Reporting out of MBA is limited.
9. MBIC provides only the MarchC+ algorithm for mbist.
The RTL for the controller logic was not synthesized for either tool to
guage the silicon "cost" of mbist. Both tools can operate from a JTAG
interface.
Having said all this, my question to ESNUG is which mbist tool would you
chose and what's your reasoning? Also could you share any experiences
you've had with these tools?
- [ Gotta Be Anon ]
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