( ESNUG 348 Item 7 ) --------------------------------------------- [3/30/00]
From: Chip Laub <chip.laub@intel.com>
Subject: Aart Says He Has No Timing Correlation Issues; We Found Otherwise
John,
I buttonholed you about the statement Aart de Geus (the CEO of Synopsys)
made in his keynote address to SNUG, claiming there were no complaints
about timing correlation between Synopsys tools. Please feel free to
publish my name, etc., on this. We have long complained about what has
been called the "Synopsys-Pathmill correlation issue". This is mainly a
problem with setup and hold time calculation at latch nodes by Pathmill.
If there are finite (i.e. slow) transition times on the clock signals
(transistor gates) controlling a latch node, the analysis is inaccurate.
Where Synopsys synthesis libraries are derived from SPICE characterizations,
any EPIC Pathmill runs on post-synthesis netlists have an ugly tendency
not to correlate well with reports from Design Compiler. We have been
pretty frustrated that EPIC (now call "Nanometer Analysis Technology" inside
of Synopsys) has not resolved this, since they agreed that it was indeed a
problem. With both Pathmill and DC now in the same company, it is even
more of a question. After Aart's bold statement, I have to ask, is this an
issue at any other design houses?
- Chip Laub
Intel Santa Clara, CA
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