( ESNUG 350 Item 5 ) --------------------------------------------- [4/27/00]
From Alan Hiren <mhirenmh@hotmail.com>
Subject: Six Headaches If You're Switching From ModelSim To Cadence NC 2.1
I am new to Cadence Affirma NC 2.1 on Solaris. Just shifted from Modelsim.
But there are many problems which I am facing while carrying out the mixed
mode (Verilog + VHDL) simulations. It would be very kind of you if you
could clear them. I am sorry to say that I have gone throught the Cadence
documentation and it was not of much help.
1. Firstly, it was difficult getting on with terms such as database
and why do we need it. Is it same as making a project in Modelsim?
Documentation says it's better to define a scope rather than adding
adding signals of a block. What does that mean?
2. I am expected to carry out the simulations in batch mode, so I would
not be opening the GUI. But then how would I be able to open a
database and open a wave file? (It was quite straightforward in
Modelsim since we just saved the waveforms and later open the do file
with a simple do command.) I could not formulate a way of saving
wave files and opening them again. My usual practice is to add
signals eveytime with simwave by opening the GUI version (I need to
open it just for this). I have heard there are lots of flexibilties
available and I would like to make the utmost use of them. Could you
please guide me on this?
3. To remove the warnings from the stdout, I have to assign a variable
set_assert_level to 'error'. But I need to do this everytime I start
a new simulation. Is it possible to assign this variable in a file
and tell simulator to source that file when invoked? But in that
case I still require to open the GUI version which I dont want.
4. Where can I get sample script files for optimal performance of the
simulator. I would like to continue using the simulator.
5. Also there are cases where I need to change the code files just for
simulating them on NC. The changes I need to do are it requires both
the IEEE as well as the IEEE_SYNOPSYS libraries to be included. More
specifically, for some VHDL files, std_logic_arith of both libraries
need to be included. For VHDL files using conv_integer,
IEEE_SYNOPSYS.std_logic_unsigned needs to be added instead of
IEEE.std_logic_arith. For VHDL files containing direct assignment of
hex value to a std_logic_vector, the conversion is required like for
instance,
signal1 <= (X"0f");
needs to be changed to
signal1 <= to_stdlogicvector(X"0f");
How do I prevent these changes to be done in my code files? Changing
the simulator version would not be a good solution since that would
not be possible in the near future and I have to continue version.
Solutions for these problems are required for this version only.
6. One more problem is I am unable to reinvoke the simulation. It says
unable to write into so and so library file... why does it try into
this library files while reinvoking the simulation. We share a
central SUN m/c. and we have the library files mapped to files in
directory where we don't have write access.
Anybody out there sailing in the same boat ?
- Alan Hiren
---- ---- ---- ---- ---- ---- ----
> 1. Firstly, it was difficult getting on with terms such as database
> and why do we need it. Is it same as making a project in Modelsim?
> Documentation says it's better to define a scope rather than adding
> adding signals of a block. What does that mean?
From: Thomas Loftus <tloftus@intrinsix.com>
I am not clear on what you mean by "database". My guess is that you are
talking about creating a waveform database and no, that is not the same as
a project in Modelsim. I think what you are reading is saying that you
need to have code in your testbench which performs PLI calls to create a
waveform database during your simulation which you can open during or after
the simulation run. Rather than call out individual signals for this
database you can indicate the scope of the hierarchy which you need to
record. That is generally sufficient so that you don't need to
indicate specific signals.
> 2. I am expected to carry out the simulations in batch mode, so I would
> not be opening the GUI. But then how would I be able to open a
> database and open a wave file? (It was quite straightforward in
> Modelsim since we just saved the waveforms and later open the do file
> with a simple do command.) I could not formulate a way of saving
> wave files and opening them again. My usual practice is to add
> signals eveytime with simwave by opening the GUI version (I need to
> open it just for this). I have heard there are lots of flexibilties
> available and I would like to make the utmost use of them. Could you
> please guide me on this
Your testbench would include an initial block which called the appropriate
$shm_open, $shm_probe type commands to create the database at the start of
simulation (or some time during it if you have a specific event to trigger
off of).
Here's a simple example. Suppose I have a testbench called tb and a device
under test instantiated called DUT. Your code to create the waveform
database would look something like (I don't have the online docs in front
of me so forgive me if this is not exactly right.)
initial
begin
// Wait for trigger event if desired
$shm_open("waves"); // Open database named "waves"
$shm_probe(tb, "AS"); // Record tb scope and all sub hierarchy
<or>
$shm_probe(tb.dut, "A"); // Record only those signals at tb.dut scope
end
This example assumes you are using the built-in waveform tool that comes
with Cadence NC (simwave, it changes to signalscan I believe with version
2.2 so this will be slightly different.)
After your simulation run, you would invoke the waveform viewer with
"simwave waves" and all the signals you asked to be recorded should be
present. You don't need the NC gui at all.
> 3. To remove the warnings from the stdout, I have to assign a variable
> set_assert_level to 'error'. But I need to do this everytime I start
> a new simulation. Is it possible to assign this variable in a file
> and tell simulator to source that file when invoked? But in that
> case I still require to open the GUI version which I don't want.
I have used specific command line switches when performing NC Verilog
compilations and elaborations which are like:
-NOWARN XXXXX
where XXXXX is a specific name shown in each warning. This lets you turn
off specific verbose messages but lets you see others. If you want to turn
them all off, I think there is a command line switch to do that as well,
but I don't know it offhand.
> 4. Where can I get sample script files for optimal performance of the
> simulator. I would like to continue using the simulator.
I have used NC Verilog quite a bit and its performance is not dictated by
scripts, but by what is being simulated, the number of PLI calls, annotation
of SDF, and many external factors like memory availability and workstation
speed. I have not found any particular sensitivity to command line options.
Probing and PLI usage should be carefully limited for maximum performance.
There are also some coding style guidelines for maximum performance which
your Cadence A/E can provide. If you want to look at performance, use the
"profile" option which is not well documented, but which creates an
"ncprof.out" file showing statistically where the simulator spends most of
its time.
> 6. One more problem is I am unable to reinvoke the simulation. It says
> unable to write into so and so library file... why does it try into
> this library files while reinvoking the simulation. We share a
> central SUN m/c. and we have the library files mapped to files in
> directory where we don't have write access.
I don't know libraries you are referring to. Perhaps an error message would
be helpful. Obviously when you compile and elaborate your design, you need
to write the resulting "snapshot" into someplace where the simulator can
read it at run time. This would have to be created in a writable place, but
once there, it would not need to be written to be run (that I am aware of).
- Thomas Loftus
Intrinsix
---- ---- ---- ---- ---- ---- ----
> 3. To remove the warnings from the stdout, I have to assign a variable
> set_assert_level to 'error'. But I need to do this everytime I start
> a new simulation. Is it possible to assign this variable in a file
> and tell simulator to source that file when invoked? But in that
> case I still require to open the GUI version which I don't want.
From: Alan Fitch <alan.fitch@doulos.com>
In Leapfrog, there is a file called hdl.var which you can put options in
which you want to have by default. It is normally located in the directory
where you launch leapfrog, but I think you can have a default hdl.var in
your home directory as well.
> 5. Also there are cases where I need to change the code files just for
> simulating them on NC. The changes I need to do are it requires both
> the IEEE as well as the IEEE_SYNOPSYS libraries to be included. More
> specifically, for some VHDL files, std_logic_arith of both libraries
> need to be included. For VHDL files using conv_integer,
> IEEE_SYNOPSYS.std_logic_unsigned needs to be added instead of
> IEEE.std_logic_arith. For VHDL files containing direct assignment of
> hex value to a std_logic_vector, the conversion is required like for
> instance,
>
> signal1 <= (X"0f");
>
> needs to be changed to
>
> signal1 <= to_stdlogicvector(X"0f");
>
> How do I prevent these changes to be done in my code files? Changing
> the simulator version would not be a good solution since that would
> not be possible in the near future and I have to continue version.
> Solutions for these problems are required for this version only.
There may be a problem here. Leapfrog/Cadence comes with a version of
std_logic_arith which is *not* the same as the Synopsys std_logic_arith!
(That's why we encourage everyone to use Numeric_std on our courses; it's
an IEEE standard).
You need to look at the code for std_logic_arith as compiled into your
library, and see if it is the cadence or the Synopsys version. If it is
the Cadence version, you need to get your computer support people to
create a different version of the IEEE library, and compile all the
packages you need into that one. You then won't be able to see the
Cadence version, hopefully.
Leapfrog 2.6 (I think) didn't support the signal1 <= X"0f" format - so
the first thing to check is that Affirma NC supports it.
Secondly, check to see if you have the VHDL93 option enabled - this
format is only valid for std_logic_vector using VHDL93. Again, you can
set VHDL93 as a default in hdl.var (in Leapfrog, anyway!).
> 6. One more problem is I am unable to reinvoke the simulation. It says
> unable to write into so and so library file... why does it try into
> this library files while reinvoking the simulation. We share a
> central SUN m/c. and we have the library files mapped to files in
> directory where we don't have write access.
You'll soon have more libraries to get Synopsys std_logic_arith :-)
You may find the date stamps are in some way inconsistent, so that
Affirma NC is trying to recompile the IEEE library as well as your own
code. For instance, std_logic_unsigned uses (SYNOPSYS) std_logic_arith,
so if Synopsys std_logic_arith hasn't been compiled, it may be that
std_logic_unsigned is complaining??
Sorry a lot of my comments refer to Leapfrog. If NC VHDL is significantly
different, I apologise in advance...
- Alan Fitch
Doulos Ltd. Ringwood, Hampshire, UK
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