( ESNUG 350 Item 9 ) --------------------------------------------- [4/27/00]
From: Nancy Nettleton <Nancy.Nettleton@Eng.Sun.COM>
Subject: Exorcist Lady Questions SNUG'00 Hierarchical Vs. Flat Survey Data
Hey there John,
Something looks funny with some of these flat vs hierarchical numbers...
> ASIC design flow ############################## 59%
> COT Cadence P&R ########## 20%
> COT Avanti P&R ########## 19%
> COT in-house P&R ### 6%
> COT "other" P&R ## 4%
Here's your break-out of ASIC vs. COT: 59% vs 49%. OK. So some people are
going both ways... I buy that.
Then you show this list of fabs:
> In-House Company Fab ############### 30%
> TSMC ############ 24%
> IBM ######## 17%
> LSI ####### 14%
> Texas Instruments ##### 11%
> UMC ### 7%
> Lucent ### 6%
> STMicroelectronics ## 4%
> VLSI, Toshiba, NEC # 3%
> AMI, Samsung, Fujitsu,
> Charter, Intel, Epson,
> Mitsubishi, National 1%
Which of these fabs have a hierarchical flow? COT shops for sure. LSI, TI,
NEC, and Toshiba are just starting to proliferate theirs. All the others
are flat as Kansas.
Oh, and your SNUG'00 data on chip sizes:
> 1 - 100 Kgates ######## 16%
> 101 - 500 Kgates ############ 25%
> 501 -1000 Kgates ############## 28%
> 1 Million + ############### 31%
Most design shops won't take a design hierarchical until its over 1M gates.
The lowest gate count I've seen on a hierarchical ASIC was 750K gates, and
that was by a rabid hierarchy monger. OK, so let's say 40% of the designs
are in the range of sizes that would benefit from layout hierarchy.
Now I get to the astounding number of hierarchical designs being done:
> Flat Only ########## 20%
> Hierarchical Only ############ 24%
> Mixed (Flat & Hier.) ############################ 56%
So 59% of the designers are designing ASICs, 69% of which are under 1M
gates. Hierarchical design flows are just starting to limp out into the
ASIC arena. And yet 80% of the designs are being laid out with some form
of hierarchy? Huh?
Something's just not fitting together here. I would expect to see some
correlation between COT and hierarchy, or chip size and hierarchy, but
this just looks like it's all over the map. If there's all this
hierarchical layout being done, what design flows are they using? COT
I can see, but not much ASIC. The flows just aren't that mature yet.
If there was this much hierarchical ASIC design out there, how come my
ASIC suppliers look at me like the Exorcist Lady when I insist on
partitioning my layout? And once I get them to partition it and they
start trying to close hierarchical timing, they look like greased pigs
on roller skates? Nope, nobody could fake inexperience THAT well.
Here's Crazy Nancy's Pet Theory: people think they're hierarchical when
they're not (like getting drunk and thinking you're funny...)
Most logic designers I've talked to who've done floorplanning had the
mistaken belief that their layout was being done hierarchically because
they could see their logic blocks in the layout. That's just not the
case. Its like seeing lines of RTL in a file and mistaking that for
logical partitioning. The layout is grouped, but its flat. It is not
partitioned such that each block can be laid out independently. Unless
the layout is truly partitioned with planned block interfaces, the
router determines how wires will enter and leave a block. You could no
more pull out that layout block and drop in another one than you could
pull out one piece of spaghetti and expect to instantiate another one
in its place.
Or maybe there's something else in the data that I'm just not seeing...
Maybe it's in the COT numbers... What do you think?
- Nancy Nettleton
Sun Microsystems Silicon Valley, CA
[ Editor's Note: I understand what you're saying, Nancy, but I have not
clear answers. I went back to the Synopsys people and had them
separate out only the pure COT people in the SNUG'00 survey and tally
their responses to the Hierarchical vs. Flat question:
Flat Only ######## 16%
Hierarchical Only ########## 19%
Mixed (Flat & Hier.) ################################ 65%
Which flies completely in the face of your statement that virtually
all of the fabs are mostly flat oriented.
And it gets weirder.
Synopsys surveyed 600 customers last year when they did the '99 update
training and asked them if they were COT or ASIC. They got:
ASIC ############################################ 88%
COT ###### 12%
And they also asked the same customers how they did design hand-off:
Netlist Only ###################### 45%
Netlist + Floorplan ############ 25%
GDS II ########### 23%
Netlist + Placement ####### 14%
Other ## 4%
"RTL Handoff" wasn't an option on the survey. The hand-off numbers add
up to more than 100 percent because some customers checked more than one
box on this question.
Why this is X-Files weird is how can 23 percent of the design hand-offs
be GDS II while only 12 percent of customers were COT then??? - John ]
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