( ESNUG 351 Item 2 ) ---------------------------------------------- [5/4/00]
Subject: ( ESNUG 348 #4 ) More User Comments On LogicVision's memBIST-IC
> 3. memBIST-IC inserts the mbist into the netlist. This has both positive
> and negative implications. Positive: Verilog porting does not need to
> be fixed through the hierarchy (the BIST adds several new ports).
> Negative: the "golden" RTL code must be frozen and the mbist inserted
> to generated the "operating" RTL code for simulation and layout.
From: Jeff Hung
Hi John,
Regarding the LogicVision memBIST-IC tool, nothing says you *have* to let it
(or more specifically, designAssemble) insert the RTL. For precisely the
reasons this designer cites, we chose to have our designers insert the
memory collars.
One feature I really wish LogicVision had is an option to pick between a
"collar" and something more like a "BIST interface". Having the collar
structure instantiate the memory sometimes didn't work in our methodology.
What we really wanted was an interface in front of the memory to handle the
BIST and functional signals. So pretty much by hand, we had to change it
from a "collar" to "interface". This ugly task is compounded by the
incredibly ugly generated code for the collar. But basically we did it
once and then forgot about it.
This approach had a number of side effects of course. After we went down
this road, we never used their synthesis scripts, nor their testbench. We
kind of had to migrate stuff into our flow, but it wasn't that bad. For
instance, because of the extremely simple controller protocol I generated
the testbench in VERA in minutes.
> 6. memBIST-IC can handle parallel or serial mbist with the number of
> comparators specified by the user. Mentor's MBistArchitect can only
> handle full parallel mbist.
This right here is the deal-breaker for us. Wire congestion was already a
problem, and full parallel bist would have been unacceptable. We used only
a handful of comparators.
What I really liked was the ease in customizing the OperationSet for an
individual memory. Since we really did want to run at speed and test time
wouldn't be a huge issue, we could modify the OperationSet to support
pipelining, and re-run the tool to get a new BIST controller. Otherwise
decoding what's going on inside the BIST controller and trying to modify it
would be a trememdous pain, given the obtuse generated controller code.
I'm sure it's that way on purpose.
In summary, we were reasonably happy with the size and wiring of BIST from
LogicVision. However, after generating the controller/collar RTL, we
pretty much went our own way.
- Jeff Hung
Silicon Spice, Inc.
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