( ESNUG 352 Item 2 ) --------------------------------------------- [5/17/00]
Subject: ( ESNUG 350 #9 ) COT vs. ASIC / Hier vs. Flat Statistical Problem
> So 59% of the designers are designing ASICs, 69% of which are under 1M
> gates. Hierarchical design flows are just starting to limp out into the
> ASIC arena. And yet 80% of the designs are being laid out with some form
> of hierarchy? Huh?
>
> Something's just not fitting together here. I would expect to see some
> correlation between COT and hierarchy, or chip size and hierarchy, but
> this just looks like it's all over the map. If there's all this
> hierarchical layout being done, what design flows are they using? COT
> I can see, but not much ASIC. The flows just aren't that mature yet.
> If there was this much hierarchical ASIC design out there, how come my
> ASIC suppliers look at me like the Exorcist Lady when I insist on
> partitioning my layout?
>
> - Nancy Nettleton
> Sun Microsystems Silicon Valley, CA
From: Gary Smith
John,
Looks like Nancy is running into a hard core issue. ;-) At least by one
definition using a hard core makes it a hierarchical design. I would think
that's what you're seeing in these responses. As far as COT vs ASIC you can
forget about the question. There are so many individual definitions for the
term COT, you'll never get a good response. There are some engineers that
insist that you need to supply masks for a true COT flow, and GDS-II doesn't
count.
- Gary Smith
DataQuest San Jose, CA
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From: Tom Ayers
To: Nancy Nettleton
Nancy,
I would suspect that some of your questions with the data would be reflected
by the following problems:
1) Quite a few design engineers have little idea of how the backend is
actually being done.
2) The survey probably did not draw a distinction in its questioning
between embedded cell ASIC layout (hard macros for memories or other
megacells), and hierarchical layout.
I suspect that combined with floorplan grouping in a flat layout and some
just confused engineers who think they have design hierarchy would throw off
the results.
- Tom Ayers
Believe.com
---- ---- ---- ---- ---- ---- ----
From: Nancy Nettleton
To: Tom Ayers
Tom,
You're right. I knew it as soon as I read the analysis. The data is still
interesting, but you kind of have to take it for what it is.
I'm hoping to see a more substantive discussion of hierarchical layout
(beyond the hierarchical vs. flat discussion). The hierarchical vs. flat
discussion is really only interesting until you hit about 2M-3M gates. Then
flat just isn't an option, and many of the hierarchical methodologies are
quite immature.
Are you seeing much in the way of hierarchical layout methodologies?
- Nancy Nettleton
Sun Microsystems Silicon Valley, CA
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