( ESNUG 353 Item 4 ) --------------------------------------------- [5/24/00]

Subject: (  ESNUG 350 #6  )   DC Synthesizing To Fewer, Bigger, Richer Cells?

> I was wondering how I could use that 23 percent white space for a few
> bigger, richer cells (e.g. AND-OR-INV) and reduce the wiring overhead.  My
> idea is while the cell area increases, the routing overhead decreases,
> and the overall design area should shrink (wishful thinking?)...  We tried
> editing the .lib file to increase the wire area in wireload model.  The
> idea being that each wire now should have an "area penalty" associated.
>
>   wire_load ("my_wire_load") {
>   resistance     :    0.000083 ;
>   capacitance    :  0.000116858 ;
>   area           :  was: 1.319252 is: 5.319252; <== but didn't help a lot
>                                                     (0.3% less nets)
>   slope          :  101.342461 ;
>   fanout_length (1, 149.84) ;
>   ... more entries here ...
>   }
>
> To me it seems that this number is primarily used for the report_area
> output but for nothing else.  Correct?
>
> We were also thinking about making nets artificially longer, so that each
> wire has a timing-penalty associated (I have no synth results yet) but I'm
> somehow not convinced that that's a good strategy.  Any suggestions?
>
>     - Christian Bohm
>       Analog Devices B.V.                        Somewhere, Europe


From: [ One Of The 47 Ronin ]

Please keep me anon.

About 6 years ago, I investigated the effect of "wire area" attribute.  At
that time we were using 0.5 um process technology and 3 layer routing was
popular.  Now most are using 0.18 um technology and 4+ layer interconnect
is common.  So I'm not sure this is still valuable, but we are still using
the same data though...

  - If you assign reasonable or realistic values for wire area, there
    is no influence on the synthesis result.

  - Assign bigger value for wire area, the synthesis result is

      1) 10% less net number
      2) 5% gate count increase
      3) 3% less layout size

This shows us that even the gate size is increased, the net number is
decreased, eventually the cell utilization is increased and final layout
size is smaller than the result with "no wire area".  Again my evaluation
data is very old, DC has many update and enhancement, but he is using 3
layer metal, so this info may be useful to him.

I also investigated the DC "porosity" attribute at the same time.  But I was
not able to find the effective result from them.  If someone has recent
evaluation result, I would also like to see it.

    - [ One Of The 47 Ronin ]


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