( ESNUG 354 Item 8 ) ---------------------------------------------- [6/1/00]
Subject: Synopsys DC 99.10 Generates SDFs With "\/" That ModelSim Dislikes
> We have a problem in the SDF file generated with Synopsys DC 99.10. We
> have a design, which we ungroup, in the lower design we have a component
> named qWRN3_F_reg in the umpi block. In the VHDL netlist generated by DC
> is umpi_qWRN3_F_reg. When an SDF file is generated using:
>
> write_sdf -c vhdl -v 2.1
>
> it appears as umpi\/qWRN3_F_reg. Our ModelSim simulator doesn't like it.
> Does anyone knew a way to overcome this?
>
> - Nitzan Poylitz Israel
From: Emmanuelle Laprise
The trick that I have found is that after you ungroup, you use the rename
command like this:
change_names -rules vst_cell -hierarchy
Where the rules can be defined something like this:
define_name_rules vst_cell -type cell -allowed "A-Za-z0-9_"
You can also use for other reaons:
define_name_rules vst_net -type net -allowed "A-Za-z0-9_<>"
define_name_rules vst_port -type port -allowed "A-Za-z0-9_<>"
change_names -rules vst_net -hierarchy
Hope that this helps.
- Emmanuelle Laprise
McGill University
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