( ESNUG 357 Item 11 ) -------------------------------------------- [8/10/00]
Subject: ( ESNUG 356 #3 ) Synopsys Formality With Scan/BIST/JTAG Issues
> You have just to remove your scan outputs, and to force your scan_enable
> to logic 0.... If you use Synopsys Formality, it can be a good way to
> reduce run-time to remove local scan on each sub-bloc:
>
> foreach all_blocs [ find_references CONT:/LIB_NAME/* -hier ] {
> current_design $all_blocs
> echo "design : $all_blocs
> foreach scan_port [find_ports $scan_enable] {
> set_constant -type port $scan_port 0
> }
> foreach scan_port [find_ports $scan_out] {
> remove_object -type port $scan_port
> }
> }
>
> On core design, we earn weeks of simulation. More than that, equivalence
> checking is very fast for verifying automated/manual IPO.
>
> - Pierre Monteil
> ST Microelectronics Grenoble, France
From: Rich Owen <richo@appiangraphics.com>
Hi John,
One point: In ESNUG Post 356, Pierre Monteil from ST suggested forcing
the scan enable to zero on all flops and removing the scan output. While
this certainly would work, it has the big disadvantage of not verifying
that the scan enable chain and enabling logic is correct. I feel the
better approach is to set the scan enable as it would under test
conditions, by forcing the enable input pin. There may be places where
Pierre's approach is needed, but it should be used as a last resort.
I agree that formal equivalency checking is vital, particularly for
multi-million gate designs. We recently used Formality very successfully
to verify large blocks that had been optimized, at times by hand.
We only ran a very tiny subset of our verification suite on the gates,
and that was largely for "peace of mind". The other advantage of
equivalency checking is that once the scripts are up (usually a pretty
fast process), equivalency checking can be run on each iteration of
the layout. You're not going to do that with simulation!
I will say, however, that debugging is a pain. The candidate list of
potential errors often just vaguely points you in the right direction.
Towards the end of the layout phase, we would debug by finding the
differences between the current and the previously verified netlist,
and then comparing that to the candidate list of errors. We didn't
find the schematic viewer all that helpful, as we had been forced
to flatten our major blocks, and generating and viewing a 100k schematic
is not pretty. But there is now way we could have found the problems
by running simulation, so equivalency checking saved us.
- Rich Owen
Appian Graphics
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