( ESNUG 358 Item 11 ) -------------------------------------------- [8/23/00]
Subject: ( ESNUG 357 #5 ) How To Initialze An Array Of Constant Integers?
> I need to inizitalise a quite large array (up to 256x256) with an array of
> constant integers returned by a function (the function generates the
> constants dependant upon some parameters in a generic list.)
>
> My problem is I believe Synopsys will only allow constants to be assigned
> integers during elaboration. Is this correct and/or is there anyway to
> get around this?
>
> - Jonathan Ferguson
> ARC
From: [ Elvis Lives! ]
Hi John,
(keep me anon)
I am previously a VHDL user. Now I am using Verilog and started facing
problems.
I wanted to instantiate an array of components. I did not find any better
way of doing that in Verilog other than instantiating each component
individially. "array of instances" is supported by simulators, but not
Synopsys.
Another problem is, in VHDL I could have a generate statement with a
generic, and instantiate any number of components during simulation.
In Verilog, I have to hardcode, because I have to indiviaually instantiate
them.
Following is an example in VHDL, I wanted to know how it can be done in
Verilog.
ENTITY comp_check IS
GENERIC (
WIDTH : integer := 3
);
PORT (
DataR : IN std_ulogic;
Addr : OUT std_ulogic_vector(Width DOWNTO 0);
Data : OUT std_ulogic_vector(Width DOWNTO 1);
);
END comp_check;
Dummy_WIDTH : FOR I IN WIDTH DOWNTO 0 GENERATE
Dummy : TECH_Dummy
PORT MAP(
A => DataR,
O => Addr[i],
AX => Data[i+1]
);
END GENERATE;
Any kind of help is appreciated.
- [ Elvis Lives! ]
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