( ESNUG 360 Item 7 ) --------------------------------------------- [11/02/00]
Subject: "W484" Logic-Munging Bug Involving DC 00.05-1 & DW Foundation Libs
> Hi, John,
>
> There appears to be a logic-munging bug in dc_shell 2000.05-1. I don't
> fully understand the bug and can't give you a small and non-confidential
> test case yet, but here's what I know:
>
> SYMPTOMS: Writing Verilog out gets error messages due to internal database
> corruption - the number of bits of a bus attached to a port of a
> designware component does not equal the the number of bits of the port.
> The Verilog netlist written is also broken and cannot be legally read
> back in to dc_shell. Neither link nor check_design finds anything wrong
> with the corrupted database.
>
> At first we thought this might be due to the user using the new Verilog
> readers described in Synthesis-713.html, since he had set the variables
> (enable_verilog_netlist_reader & hdlin_enable_presto) to enable them.
> However later we saw the bug in cases where those variable were not set.
> So, this is probably irrelevant.
>
> The bug seems to be related to DesignWare add/subtract/increment/decrement
> elements, and has only been seen in situations where the RTL gives a
> Verilint W484 warning. We were using DW Foundation, so that could also be
> a factor.
>
> W484 warnings are seen when the receiving variable for an add or subtract
> result does not have enough bits to hold all possible resulting values
> (carry or borrow is lost). For example, I often see coding like:
>
> reg [7:0] a, b, c;
>
> c = a + b;
>
> This isn't quite right because the sum of 2 8-bit numbers may take 9 bits
> to hold, and Verilint correctly complains. If you change it to:
>
> reg [7:0] a, b;
> reg [8:0] c;
>
> c = a + b;
>
> then the warning goes away. Changing our Verilog source code to eliminate
> the W484 warnings eliminated the problem, i.e. it apparently no longer
> triggered the bug.
>
> RECOMMENDATIONS: Until we know exactly what's causing this bug, I would
> recommend that you:
>
> (1) Run Verilint on your input Verilog RTL, and fix it to eliminate any
> W484 warnings.
> (2) Write out a Verilog netlist even if you don't need it, and make sure
> you have no error messages.
> (3) As a double check, read the Verilog netlist back in and make sure it
> succeeds.
> (4) If you're still nervous, go back to an earlier dc_shell. This bug
> does not seem to occur in 1999.* versions.
>
> Those of us who routinely get our Verilog RTL squeaky clean with respect
> to Verilint, and thus don't have any W484 warnings, can feel smug compared
> to those who routinely ignore such warnings because they can't be bothered
> with picky details like that when they have a chip to get out. :-)
>
> More as soon as I have time. Unfortunately, since we've worked around
> this bug already, it's not my top priority.
>
> - Howard A. Landman
> Vitesse Semiconductor Longmont, Colorado
From: [ The Synopsys Support Center ]
Hi Howard,
This is regarding your DW problem. I've searched our database, and I
believe I've found a match on your case. I believe you got the error
message VO-5 when you wrote out your Verilog netlist. Is that true? If
so, there are a number of STARs filed on this and the problem is fixed
in our next release 2000.11. The current workaroud is to set the
variable: compile_disable_hierarchical_inverter_opt to true. Hope this
also solves your problem.
- [ The Synopsys Support Center ]
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