( ESNUG 360 Item 10 ) -------------------------------------------- [11/02/00]
Subject: ( BSNUG 00 #5 ) 7 Silicon Perspectives First Encounter Tape-outs
> We had a visit from our friendly Silicon Perspective sales team today and
> the demo they showed sparked some interest. They claimed to have several
> tape-outs under their belt at this point, which is when I thought, "Yeah,
> but have you told Cooley about them yet?". Heard any more from the
> masses on this one? Their "don't flatten the hierarchy" approach to floor
> planning certainly has some major benefits. Just thought I'd look for
> some further references before engaging in any kind of benchmark.
>
> - Pete Churchill of Conexant Systems
From: Stefan Thiede <Stefan.Thiede@sv.sc.philips.com>
Hello John,
We were one of the customers which used Encounter for our tapeout.
Our chip contained 1,200,000 stdcells which we repartitioned with in-house
Philips tools into 8 "chiplets" (Blocks large enought to be called chips :-)
plus 2 CPU-cores. The chiplets varied in size from 65,000 to 210,000
stdcells.
We've used Silicon Perspective to find the optimal placement of our 200+
macros, for placement, and IPO.
The feedback from the "amoeba" placer was extremely helpful to find good
macro placement due to it's unique visualization of hierarchy. The placer,
though slower than competing products, produces a more porose placement
that allowed us to use their real gem, their IPO capability, without
screwing up the routablility. This also helped during clk-tree insertion.
The IPO resized (up/down) ~25% of all cells in the design based on
Encounter's estimated routing and was able converge on timing. The runtimes
per chiplets for IPO were very short compared to the other options we had.
This is a placement-based optimization that actually works and it's fast.
Encounters timing engine reads constraints from PrimeTime and is extremely
fast. Verilog-in/out/flattening/defout/tdfin/out all run in ~10 minutes on
the full chip.
For the next tapeout, we'll use Encounter for full-chip placement-based
timing analysis. It is capable of holding the whole placed and routed
design in 1.7GB process size. This compares to 1.8GB for a 210,000 stdcell
block in Apollo.
We are going to have a look at Encounter's hierarchical pin assignment and
their clk-tree synthesis. We are specifically eager to lay our hands on
their feedthru capabilities, due later this year.
In our experience, Encounter did what it promised, does it fast, and has the
capability to handle full-chips of 1+ million stdcell instances.
- Stefan Thiede
Philips Semiconductors Sunnyvale, CA
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From: Mano Vafai <mano@klsi.com>
Hi, John,
I would like to invite you or any serious ASIC designer of your community to
visit Kawasaki LSI's Silicon Valley office so we could explain our usage of
Silicon Perspective's First Encounter tool in our production ASIC flow.
Silicon Perspective floorplanning and placement tools has helped establish a
missing link between Synopsys DC, and Cadence Silicon Ensemble (SE). This
allows our ASIC customers to leverage their existing investment in front-end
Synopsys environment and us at KLSI to utilize SE more efficiently. We also
make use of floor planning tools like Avanti Compass, Cadence PDP, and
Synopsys Gambit. However their scope is limited to CBA (Synopsys's Cell
Based Array) or some other low complexity Standard Cell designs.
Kawasaki has benchmarked a few other tools such as the ones developed by
Monterey and Magma. However we particularly selected Silicon Perspective
because of its front-end design orientation, super fast execution, and
excellent timing correlation with both SE and PrimeTime. In doing so,
Silicon Perspective tools really helped us to tape out a very complex
Networking ASIC on time.
- Mano Vafai
Kawasaki LSI San Jose, CA
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From: Tony Liu <tonyliu@sis.com.tw>
Hi, John,
We were one of the customers which used Encounter. And We've successfully
take the advantage of First Encounter for two tapeouted projects. One of
them is 1.2 million placed object, and the other one is more than 800K
placed objects. We appreciate the hierarchically partition and pin
assignment of First Encounter.
It really do a good job for those.
The placement of First Encounter also make our project a good initial point
for timing closure. We appreciate this tool in many aspect, and
contineously find out more advantage.
- Tony Liu
SiS Taiwan
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From: Sunil Malkani <SunilM@teralogic-inc.com>
John,
I manage the Physical Design and CAD team at TeraLogic. I wanted to confirm
that we have used SPC's First Encounter for two of our chips one which taped
out about a year ago and the other taped out May 2000.
The first chip was running at 108 MHZ worst case, process was TSMC 0.25
4-Metal. The second chip was running at 120 MHZ, TSMC 0.25 5-Metal.
In the first chip, which was hierarchical, we used Encounter on one of the
blocks which was having problems in achieving timing convergence. The block
was about 80K placeable cells and also included 4 large memories. Encounter
worked pretty well in floorplanning the block and achieving better timing
results than our existing tool at that time -- it had a big advantage in
turn around time so we could do multiple what-if scenarios.
The second chip had 450K placeable cells and FE was used just for the IPO
part using the existing placement. Also the front end team used the tool
to evaluate different floorplans to get a quick timing view.
- Sunil Malkani
TeraLogic, Inc.
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From: Tom McKeone <Tom.McKeone@amd.com>
Hi, John,
I am a product development manager that works in the AMD chipset department.
We have successfully used First Encounter on two different tapeouts in the
last 9 months. The tool did a fantastic job for us. The design contained
over 650K placable instances & had multiple clock domains that ranged from
66Mhz to over 533Mhz. Encounter handled this complex design expertly. It
was able to optimize timing as well as provide estimated timing in a very
short period of time. The estimated timing was amazingly accurate. We found
it to be within a few percentage points of the timing data extracted from
the final routed design. (We used Apollo (version 1999.4.3.3.0.14) from
Avanti for routing this chip.)
The tool is continuously improving. On the last tapeout we used their spare
gate "shotgunning", scan re-ordering, and clock tree synthesis. Overall
the results were very good and the time savings significant.
- Tom McKeone
Advanced Micro Devices Texas
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