( ESNUG 363 Item 7 ) --------------------------------------------- [01/25/01]
From: Daniel Geist <geist@il.ibm.com>
Subject: Can DC Shell Circuit Optimizations Be Disabled For IBM Designs?
Good Day John,
My name is Daniel Geist. I am in charge of the development of IBM's model
checking tool which is used both in IBM and also sold to a few customers
outside IBM. We have a problem with a few external customers. We have our
own Verilog compiler for Solaris but our VHDL compiler runs exclusively on
AIX. Porting to the VHDL Compiler to Solaris will be a major effort so we
suggest to our customers that use Synopsys in their design flow to do the
following:
1. Use dc_shell to compile their code and translate it to a very
simplified gate-level VHDL.
2. Use a small utility we supply to read in the simple format into
our tool.
There are two problems with this solution.
A. Minor: Its not seamless and from time to time the details have to be
reworked due to changes in newer versions of dc_shell.
B. Major: No matter how much we have tried to control dc_shell it
continues to lose signal names from the original design in the
translation. Since our tool produces counter-example (error traces)
the users that have to debug them are quite annoyed since they have
to guess what the trace implies about the missing signals (which
get renamed to some generic name). It can prolong the debugging time
from minutes to hours.
The Synopsys support team has looked into this problem (B.) and basically
said there is no good solution. We also tried using dc_shell to translate
to Verilog and using our Verilog compiler. That actually improved the
situation considerably. However, Synopsys support said that its not the
way to do it which worries me .
I thought before we tried to go into another perhaps costlier solution your
readers may be able to assist in this matter.
- Daniel Geist
IBM Haifa Research Lab. Haifa, Israel
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