( ESNUG 364 Item 13 ) -------------------------------------------- [02/01/01]

From: Sai Kishore R <skishore@virtualipgroup.com>
Subject: Is An All NAND Or NOR Gate Lib The Best Lib For Design Compiler???

Hi John,

This is observation on one of my design.

  1. I compiled the design with normal techniques using Design Compiler.

  2. I compiled the same design by putting set dont_use attribute on all
     cells except NAND and NOR gates.  I got good timings with less area
     compared to the previous case.

Is it a unique case for my library or true for all libraries?  If it is
true, why bother with other cells?  Do you have any idea about this?

I tried this with a 16-bit multiplier in WSMC 0.25 technology.

    - Sai Kishore
      Qualcore logic ltd.
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