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( ESNUG 364 Item 15 ) -------------------------------------------- [02/01/01]
Subject: ( ESNUG 363 #14 ) Pass-Thrus In Hierarchical Physical Designs
> We are having our first experience with a large hierarchical design and
> are trying to find the best way to handle global routing of signals that
> cross blocks. We don't think the top-level routing ability of Apollo will
> do a good enough job, and it also won't allow us to place buffers or flops
> where we need them. We are thinking instead of embedding pass-thrus in
> different blocks where needed to better facilitate the travel of these
> global signals across the chip. As best we can tell, this will require
> adding the pass-thru connectors (and flops if we use them) to the RTL of
> the blocks containing the pass-thrus. However, we'd prefer not to mess
> directly with the RTL that the designers are working with.
>
> One idea we had was to put wrappers around the top-level RTL blocks
> and add the pass-thru's (and flops if needed) to the wrappers...
>
> - Jeff Winston
> Conexant Systems
From: [ Puff, the Magic Dragon ]
Hi John,
First of all, please keep me anonymous.
One proven way to handle top level net timing is to insert repeaters on a
wire length base. This means that you insert a buffer every X um of wire.
The number is calculated such that the transition at the input of the
receiving buffer won't be less than your max_transition rule assuming a
typical transition time at the input of the transmitting buffer.
Now, you can think of two cases:
1. You have channels between the blocks, where the top level nets route.
In this case you should put these repeaters in the channels. This is
tricky, since usually you don't have placement regions there, and
connecting the buffers to the supplies isn't automatic.
One way to overcome this is to always define some placement regions
at the top level, around the blocks.
2. You route the top level nets through the blocks. In this case, adding
the buffer is easy. You just preplace the buffer where you want, and
let the P&R do the rest.
Best Regards,
- [ Puff, the Magic Dragon ]
( ESNUG 364 Networking Section ) --------------------------------- [02/01/01]
San Diego, CA -- Magis Networks (pre-IPO) needs layout & verification gurus
for high-speed wireless home networking chips. "gbell@magisnetworks.com"
Marlborough, MA -- Axiowave Networks (pre-IPO) seeks ASIC and board-level
design and verification engineers. No headhunters. "ewhitney@axiowave.com"
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