( ESNUG 366 Item 10 ) -------------------------------------------- [02/23/01]
From: Lars Rzymianowicz <larsrzy@ti.uni-mannheim.de>
Subject: We're Having Some Troubles With The Synopsys DWPCI v3.4b Core ...
Dear John,
First of all, thanks for running ESNUG! Every new post makes my day. ;-)
We just plugged in the Synopsys DWPCI v3.4b core into our design.
Everything's fine, with one exception: in the PCI Config Header, the first
16 words are device independent (command, status, BAR regs, etc.) We can
read/write them in the simulation via PCI config cycles. Fine. After these
regs, there is space for up to 48 user device-dependent registers, starting
at adr x40. Via the parameter 'cfg_num_dev_regs' (device-specific
registers) you can define, how many regs you would like to use. We set it
to 4, and we verified, that these regs show up in the generated netlist.
But we can't write these regs via PCI config Cylces. All following reads
return 0.
We analyzed the netlist (we only have encrypted sources, so we have to load
the netlist into Design Analyzer and look at the gates) and found out, that
the 'enable' of those config DFFs can never be true! Its fanin logic is
sth like 'A and NOT_A and ...' We observed all interface signals to the
config module, and they match the signals from the manual (dwpci.pdf, Sec
5-31ff, Accessing Configuration Space Registers). So the question now is:
is there any parameter, which blocks write access from the PCI side to these
regs? Is this a bug? Or what?
We'd appreciate any help from other DWPCI users!
- Lars Rzymianowicz
University of Mannheim Mannheim, Germany
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