( ESNUG 368 Item 6 ) --------------------------------------------- [04/12/01]
Subject: ( SNUG'01 #26 ) SystemC Is A Lot Of Work For What Little It Does
> When our SW guys need what we're working on for their simulations, we
> tranlate it over to C, bottom up. SystemC works, but it's ugly. It's
> a solution in search of a problem we don't have. We'd rather do our
> hardware design in Verilog and then translate it to C at the last minute
> when it's needed by the SW guys. Verilog is much more graceful for
> hardware design. Translating it to C is easy.
>
> - Martin Gravenstein
> TDK Semiconductor Corp.
From: Ken Merryman <Kenneth.Merryman@unisys.com>
John,
I see no use of the C based languages here for at least two years (if ever.)
We have been simulating large systems for years with the our proprietary
languages, then VHDL and now Verilog. Our high level architectural system
simulation uses a queuing language and does not need to actually perform the
logical functions as required for design verification. For what we design
it's hard to see the connection between architecture modeling and design
implementation.
- Ken Merryman
Unisys Roseville, MN
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