( ESNUG 370 Item 9 ) -------------------------------------------- [05/17/01]
From: Gregg Lahti <gregg.lahti@corrent.com>
Subject: Module Compiler, DC-Tcl, & Presto Don't Play Nice With Each Other
Hi John,
We've found a weirdness using DC 2000.11 and a combination of Presto,
dc_shell-t (Tcl), and Module Compiler. If we enable all three items, we
get errors at the "elaborate -gate_clock [module]" phase. The reports
generated during the elaboration don't provide any clock gating
information and then the error pops up at the end of the elaboration:
Error: Module Compiler License is not available; aborting
insert_clock_gating. (PWR-352)
Go to DCSH or disable Presto and the problem goes away. I would suspect
that this problem was masked when we had an Module Compiler license and
then this reared its ugly head when our Module Compiler license expired.
Anyone else see weird issues like these with Presto and Tcl?
Also, has anyone experienced issues of MC corrupting the synopsys_cache
with psuedocells? We were experimenting with MC and wound up getting
"cannot use estimated timing" error messages when we wrote out to a DB
or Verilog file. We tracked it down to a corrupted cache, but I couldn't
figure out if MC corrupted the DW components or if DC incorrectly grabbed
the psuedocells generated from MC. Clearing the cache resolved the issue
via brute force, but that seems overkill and a waste of compute resources
for future issues.
- Gregg Lahti
Corrent Corp. Tempe, AZ
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