( ESNUG 371 Item 16 ) ------------------------------------------- [05/23/01]
From: John V. Harding <j.harding@motorola.com>
Subject: The Prepended X Problem In EPIC Amps & Synopsys EPIC Tool Support
John,
What follows are excerpts from an e-mail dialog between Synopsys support and
myself about an issue we saw with Amps version 5.5.
[Me to Synopsys]
Amps produces incorrect instance names in SPICE.
I ran Amps with the -S switch to produce a SPICE netlist from a Verilog
netlist and an STW file.
If there is an instance name in the Verilog netlist that begins with the
letter "x" the SPICE generated using AMPS is incorrect. Instance names
in SPICE have an "X" prepended on the Verilog instance name, however,
when that instance name begins with "x" AMPS does NOT prepend the "X"
like it should.
[Synopsys to me. Note the reference to marketing]
I double check EPIC netlist compiler behavior and found that for Verilog
netlist, our netlist compiler will drop leading X in the instance call.
If there is no leading X for instance call, then netlist compiler will
add an extra X to fit SPICE syntax.
For example, I write a simple test module like:
module top;
and1 XI1(1, 2, 3, 4);
and2 XI2(5, 6, 7, 8);
And netlist compiler will translate to
.subckt top
XI1 1 2 3 4 and1
XI2 5 6 7 8 and2
.ends top
And I did another test without leading X for instance call
module top;
and1 I1(1, 2, 3, 4);
and2 I2(5, 6, 7, 8);
endmodule
And netlist compiler will translate to
.subckt top
XI1 1 2 3 4 and1
XI2 5 6 7 8 and2
.ends top
Note that with/without leading X for instance call, EPIC netlist compiler
will give identical SPICE netlist. This is our internal algorithm to
compile Verilog netlist and if you want to see double Xs in the output,
then we need to file an enhacement request and go through marketing
review. But I do have question on with/without leading X, does the AMPS
output create any trouble in your follow up simulation flow?
[me to Synopsys]
What result will I get if my Verilog netlist was as follows:
module top;
and1 I1(1, 2, 3, 4);
and2 XI1(5, 6, 7, 8);
endmodule
[Synopsys to me.]
I tested in the netlist compiler and turns out:
.subckt top
XI1 1 2 3 4 and1
XI1 5 6 7 8 and2
.ends top
This will be a issue of duplicate instance name. I have initial a discuss
with marketing person and she said it will be difficult to prioritize this
issue as high as you expect. So we are wondering can this issue be solved
at Verilog coding phase? But anyway I will file an enhancement request on
this one.
[Synopsys to me, again]
I have filed a bug under bugid 117180. I will update you ASAP once I hear
back from marketing/R&D team. But I would expect a longer turn around
time.
End of saga. (Well, not really...)
- John Harding
Motorola StarCore Atlanta, GA
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