( ESNUG 373 Item 10 ) ------------------------------------------- [06/07/01]
Subject: ( ESNUG 371 #1 ) PhysOpt's Placement Of Clock Gating Cells
> I have some preliminary data to report on PhysOpt and clock gating cells.
> We're not using integrated clock gating cells, which makes this case
> *very* interesting for us.
>
> Around 71% of the clock gates have less than 10 um between the main gate
> and the enable latch. Here's how PhysOpt placed them:
>
> < 10 um - #################################################### 105
> 10 to 20 um - ################ 32
> 20 to 30 um - #### 8
> 30 to 40 um - # 2
> > 40 um - 0
>
> Total clockgates 147
>
> I can provide more info later if you'd be interested... I'm curious to see
> how our router handles these.
>
> - Neel Das
> Corrent Corporation
From: Lars Bo Graversen <larsg@mips.com>
Hello John,
I read Meel's ESNUG Post with great interest as it seems like he is using a
somewhat similar approach to clock gating with PhysOpt as we are. In
particular, I am interested in his statistics of the placement of the latch
with respect to the main clock gate. Has he generated this information
using a script? If so, would he be able to share this script with us? I
would like to attempt to generate the same type of statistic for our design.
- Lars Bo Graversen
MIPS Denmark
---- ---- ---- ---- ---- ---- ----
From: Neel Das <neel.das@corrent.com>
John,
I'll see what I can do. I'm disappointed so far with CTS results, though...
Lars, do you have any data in that realm that you could share?
- Neel Das
Corrent
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