( ESNUG 374 Item 2 ) -------------------------------------------- [06/14/01]
From: Cliff Cummings <cliffc@sunburst-design.com>
Subject: Cliff Unabashedly Pimps Superlog For Next Week's DAC Conference
Hi, John,
Your ESNUG readers might want to catch one of the Superlog demos at DAC to
find out why five members of the Verilog Standards Group, myself included,
have joined the Superlog working group in the past year.
Four of us attended a Superlog demo at HDLCON last year and were very
impressed because Superlog is going to be a super-set of the Verilog-2001
language -- including features that we never were able to pass for the
Verilog-2001 Standard. At the request of one company, I even taught a
Verilog class this past year using the Superlog simulator. The only lab
that we could not do in my Verilog class was the SDF lab, but I believe SDF
will be implemented soon by Co-Design (I was very impressed!)
In this past year, the Superlog Working Group added a number of constructs
to enhance synthesis capabilities. Another booth that I plan to attend is
the Get-2-Chip booth, to see what David Knapp (author of the Behavioral
Compiler book and SLWG member) is doing about Superlog synthesis.
On Thursday, June 14th, Vassilios Gerousis is holding the first Accellera
meeting at Mentor, San Jose, to kick off a Verilog++ effort, where the
Co-Design Superlog synthesis subset and the Verplex OVL are supposed to be
donated. I plan to attend.
I will let you know if I feel this effort is going to be successful or if
it is going to implode like the SystemC committee.
- Cliff Cummings
Sunburst Design Beaverton, OR
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