( ESNUG 376 Item 1 ) -------------------------------------------- [08/29/01]
Subject: ( DAC 01 #25 ) Well, We're Happy With Ambit-RTL/Get2Chip/Synplify
> Get2chips, Synplicity, Incentia, and Ambit all have the same flaw: they're
> "me, too" tools. The best they can do is to catch up with DC -- they're
> just re-solving an EDA problem that's already fully solved. PhysOpt, PKS,
> and Magma are where the real battle is being fought these days.
From: [ Silent Bob ]
John please use the following comments anonymously!
Synplify ASIC is a great tool. I've used it to compile large designs, with
very fast runtimes and quality comparable to Synopsys Design Compiler.
Synplicity is aiming this at their existing customers, most of whom do ASICs
as well as FPGAs. Until now this has required two sets of design tools. It
was hard for one engineer to be proficient in both ASIC and FPGA flows. Now
a single front-end can be used for both.
Argument against Synplicity: "You guys must be crazy to go up against
Synopsys! You'll get killed!"
Answer: "We've been competing against them for quite a while in the FPGA
market, and doing very well at it, thank you."
Keep you eye on the silicon vendors that Synplicity announces support for.
This will tell you what sort of customers they are selling to. If you
see support for cutting-edge SoC libraries, watch out Synopsys!
- [ Silent Bob ]
---- ---- ---- ---- ---- ---- ----
From: Mike Bly <Mike.Bly@worldwidepackets.com>
John,
The team I work with used to be Synopsys-based, but we've since "seen the
light" :), and gone to Ambit. Ambit is far more cost-effective, and during
our evals/compares between the two, we found more plusses for Ambit over
Synopsys, than the other way around. Ambit seemed to build better/faster
/smaller logic in less time, over a variety of designs. I guess
cost-effective is a major point still, allowing you to have many Ambit
licenses for developers to use to check their designs with. More and more
people are going deeper into the backend, using tools like PKS, etc. to do
their actual final synthesis, so it doesn't make sense to drop the cash on
base-synthesis Synopsys licenses anymore.
- Mike Bly of World Wide Packets
---- ---- ---- ---- ---- ---- ----
From: "Steve Golson" <sgolson@trilobyte.com>
Hi, John,
I'm very impressed with Volare synthesis from get2chip. Large capacity, fast
runtimes, great quality of results.
When Ambit first showed up, they had a great deal of cockiness bordering on
arrogance. We're going to take over the synthesis market! Synopsys is
doomed! Aren't we cool! Get2chip has a refreshingly different attitude.
They have quiet confidence in their tools and are letting the results speak
for themselves.
Get2chip's support for Superlog is another huge point in their favor. If I
want to use this neat new language, get2chip is the only synthesis game in
town (for now). The fact that I can get really outstanding results on legacy
Verilog code is icing on the cake.
One argument against get2chip is that ten-plus years of testing Synopsys
Design Compiler has wrung all the bugs out. You know DC won't make bad
gates. Nobody ever got fired for buying Synopsys synthesis tools. So how does
a newcomer like get2chip overcome such an argument? Formal verification is
the answer. Use Volare from get2chip for synthesis, and use a formal
equivalence checker to verify correct gates.
(Note this was also an argument against Ambit. But Ambit was too early;
formal verification was not accepted when they tried to crack the DC market.)
Also the get2chip Topomo tool looks like an outstanding front-end synthesis
engine to feed Synopsys PhysOpt. Nobody else has shown a workable flow for
how to synthesize multi-million gate ASICs and partition them into the
150k-gate blocks that PhysOpt requires.
See, these guys really do like Synopsys! :-)
- Steve Golson
Trilobyte Systems Carlisle, MA
|
|
