( ESNUG 376 Item 9 ) -------------------------------------------- [08/29/01]
Subject: ( DAC 01 #23 ) Screw FastScan & TetraMax; I Want IBM Vectorless!
> MENTOR ON THE ROPES: Three months ago, Gary Smith of DataQuest reported
> that the '99 DataQuest numbers gives Synopsys 52.2% vs. Mentor 24.0%
> marketshare in the ATPG business. "I see Physical Compiler driving the
> dominance of Synopsys in the DFT market, and Mentor's marketshare should
> continue to shrink," said Gary at the time. Sad news for Mentor, because
> years ago, they used to have a really good rep with the high priests of
> chip test. And Synopsys Test Compiler used to be the Tool-That-Everyone-
> Bitterly-Complained-About. It's odd how the wheel of fortune can turn.
From: "Hank Walker" <walker@cs.tamu.edu>
Hi, John,
TetraMAX and FastScan I would say are similar in that each has some nice
feature the other doesn't have, each has some drawback the other doesn't
have, and neither seems to have such a great advantage over the other to
make it worthwhile to switch if already using one.
IBM Testbench is available to users and has some nice features the others
don't have, like pattern faults and pattern fault diagnosis. These tools
are still best able to handle digital ASICs, and can still require some
non-trivial modeling effort to handle custom designs such as CPUs.
I would say the #1 thing I would want in all of them is more flexible
access to the internal engines, e.g. via a Tcl interface, so that that the
expert user or internal support group can try to resolve their own issues
without waiting for a new feature. This also makes it easier for the
developers to try a new feature with a lower-performance interface before
wiring it into the guts.
The ideal from the designer viewpoint is still IBM's vectorless release
for their ASICs. Just let the foundry worry about it. But the tradeoff is
the need to follow the specific flow to permit this.
- Hank Walker
Texas A&M University
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