( ESNUG 378 Item 11 ) ------------------------------------------- [10/03/01]
Subject: ( ESNUG 377 #17 ) How To Create DC Statistical Wireload Models
> I searched in your deepchip web site and could not find any discussion on
> how statistical wireload model is generated, step by step. I have read
> Synopsys available on-line manuals, searched SolveNet, and asked my
> Synopsys AE. No document or AE can answer it. Help!
>
> - Chia-Lan Li
> Medtronic, Inc. Tempe, AZ
From: [ An Arizona Synopsys FAE ]
Hi, John,
I can tell you from my experience there is no standard way of generating
statistical wireload models. What the Synopsys documentation provides you
is the syntax and the way that the information is used in the timing engine
and then the vendors are responsible for figuring out how to come up with
the numbers for their technology. The most common way to generate models:
1) Gather as many designs as you can from within your user community
of your given technology. (This seems to be the biggest issue is
getting enough designs to get a good distribution of information.)
2) Take blocks of a given size of design, plot out the wire length
per number of pins on the net minus 1. (This is to eliminate the
driver itself.)
3) Plot out the median value in the distribution points to include in
your statistical model (you may need to throw out some values that
fall way out of the model.)
4) Use these values to plug into your models.
The biggest problem with statistical wireload models is that they usually
don't represent the specific design you are working on and it is very
dependent on getting enough data points. The process can be very time
consuming to gather all the information and the information does not scale
in a predictable way from technology to technology. Another problem is
that most tables are generated assuming a square area when often the actual
block in the floorplan may have a rectangular or rectilinear shape which
makes the estimates even farther off. As the technology gets smaller and
smaller, and the net delays become more and more of a factor, every amount
of delay estimation that is incorrect makes it more difficult to come
to timing closure. The wireload models do not account for other
obstructions the design may encounter in the floorplan as well.
- [ An Arizona Synopsys FAE ]
---- ---- ---- ---- ---- ---- ----
From: Edmond Macaluso <edmond@z-circuit.com>
John,
Normally, you take a previous design or a part of a design that is
representative, compile it, do a quick P&R, extract, created SDF, Set_load
and then build WLM's from this.
You can then use this for the initial compiles of new RTL. Once you
get compiles of the design, build custom models for it. I think the word
"statistical" is a bit mis-leading. Look at Golson's "Resistance Is
Futile!" paper on building wireload models #28 in the DeepChip's Downloads.
It is a useful paper. Also, look at Synopsys Floorplan Manager manual which
is pretty good. It has all sorts of methods for building and assigning
wire-load models. Synopsys also supports "sticky loads" for long nets
which help a lot.
I teach a flow training workshop through Artisan Components and this is one
of the topics we cover.
- Edmond Macaluso
Z Circuit Automation Mountain View, CA
---- ---- ---- ---- ---- ---- ----
From: [ A Synopsys CAE ]
John,
A fair amount of research work exists on both effectiveness and derivation
of accurate wireload models. Bottom line though is that calibration of
initial wireload is highly dependent on design style (lots of busses vs.
random, lots of global signals vs localized), layers of metal available and
your choice of placer/router(s). When all is said and done, you need to
base wireload models on as many statistically relevant (similar process,
metal, design style) finished chip data sets as possible.
Some references:
http://www-device.EECS.Berkeley.EDU/~dennis/papers/iccad98.pdf
http://www-device.EECS.Berkeley.EDU/~dennis/papers/tau99.pdf
http://www-device.eecs.berkeley.edu/~dennis/bacpac/models/delay.html#wire_model
W.E. Donath, "Placement and average interconnection lengths of computer
logic," IEEE Transactions on Circuits and Systems, vol. 26,
pp. 272-277, April 1979.
A. Masaki and M. Yamada, "Equations for estimating wire length in
various types of 2-D and 3-D system packaging structures," IEEE
Transactions on Components, Hybrids, and Manufacturing Technology,
vol. 10, pp. 90-198, June 1987.
J.A. Davis, V.K. De, and J.D. Meindl, "A stochastic wire-length
distribution for gigascale integration (GSI) - part I: derivation
and validation," IEEE Transactions on Electron Devices, vol. 45,
pp.580-589, March 1998.
In addition there is also a SNUG'99 paper on wireload models "Resistance is
Futile! Building Better Wireload Models" by Steve Golson.
Hope this helps.
- [ A Synopsys CAE ]
---- ---- ---- ---- ---- ---- ----
From: Chia-Lan Li <cli@tmp.medtronic.com>
Dear John,
I am using Golson's approach and scripts to examine the wire load model I
generated from Synopsys and Cadence HyperExtract. I am also trying to
compare how different in timing/area when using table format and standard
format wire load model. HyperExtract generates standard format WLM while
Synopsys generates both table and standard format WLM. Synopsys Floorplan
Manager User Guide indicates table-format models are more accurate than
standard format models (p.4-9).
After sorting out which tool and which format WLM to generate, I'll try
the approach suggested by the Synopsys Arizona FAE.
There are two new papers coming out which I think are worth reading. One is
from Boston SNUG 2001 by Duane Galbi and Dwight Galbi, "Improved Interconnect
Modeling using Path Based Time Budgeting Instead of Wire Load Models". The
other is to be published at ICU 2001 by Kenneth Boese, Andrew Kahng and
Stefanus Mantik, "On The Relevance Of Wire Load Models".
Thanks John for your well organized ESNUG so we can have a place to research
and post questions.
- Chia-Lan Li
Medtronic, Inc. Tempe, AZ
---- ---- ---- ---- ---- ---- ----
From: Jerry Gebhard <jerryg@intimesw.com>
Hi, John,
I work for InTime Software. Our tools are used before synthesis, during RTL
development. DesignWarrior allows designers to predict performance and area
before running CPU-intensive DC runs. This allows a designer to look at
many more RTL architecture variations before deciding on the final one to
use for physical implementation.
We automatically create custom wireload models and design specific "set
load" parasitic files for your DC runs.
- Jerry Gebhard
InTime Software Austin, Texas
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