( ESNUG 379 Item 16 ) ------------------------------------------- [10/11/01]
From: "Mike Montana" <montana@synopsys.com>
Subject: A Useful PhysOpt Script For Pulling Tri-state Drivers Together
Hi, John,
We're seeing more ASICs using that "wonderful" design feature called an
internal tri-state bus. I use "wonderful" because optimizing tri-state
busses to meet timing and design rules is a real challenge for DC and
PhysOpt. You can't simply go in and add buffers to fix problems on a
tri-state net. And in some libraries, there may only be 1 internal tri-
state driver so cell sizing is not even possible. The only solution for
this problem is to make sure all the drivers on a tri-state net are placed
close enough together to avoid timing and design rule violations.
In the past, this was a manual task done in the back end. But with PhysOpt,
you can eliminate these tri-state issues before handing off the netlist to
route. But you must "prioritize" placement of the tri-state drivers
relative to the other cells in the design if you're using PhysOpt.
The script attached was created by an AC here in Dallas working with a local
PhysOpt customer. Here's how it works:
1) The script parses the netlist to identify all the tri-state nets
from the net attribute "three_state."
2) Once these nets are identified, the script finds all of the gates
that drive each tri-state net.
3) Finally, the script groups these gates into a movebound. A movebound
is a floating soft region. PhysOpt can place the cells in the
movebound anywhere on the die based on timing, DRC, and congestion
rules while also keeping them close together. (See the man page
for the set_bounds command for more user options.)
The script outputs a movebound for each group of cells driving tri-state
nets in the design. The script does not define a size for the movebounds,
but rather assigns the movebounds with a level effort high. PhysOpt uses
an internal algorithm to size the movebounds and it places the gates
accordingly. Other effort levels for the movebound command are also
available (low, medium or ultra) to control how tightly the cells are
grouped.
The result, the cells attached to each tri-state net are pulled close
together eliminating timing and DRC violations.
- Mike Montana
Synopsys Dallas, TX
#
# TCL Procedure to constrain tri-state cells to be close to each other
#
proc tri_state { } {
echo "Started- procedure tri_state [date]"
suppress_message UID-95 ;# warnings for dummy cell below
# initialize counter for number of bounds
set count 0
# create the flag to signal continuation of procedure
exec touch .go
set all_tri_nets [get_nets -hier * -filter "@three_state == true"]
set number [sizeof_collection $all_tri_nets]
echo "There are $number tri-state nets in this design"
# itterate through the nets to make a collection of pins
set all_tri_pins [add_to_collection {} {} ];# start empty collection
foreach_in_collection mynet $all_tri_nets {
set all_tri_pins [add_to_collection -unique $all_tri_pins \
[all_fanin -flat -levels 0 -to $mynet]]
set all_tri_pins [add_to_collection -unique $all_tri_pins \
[all_fanout -flat -levels 0 -from $mynet]]
# check for the existance of the go flag to continue the procedure
if {![file exists .go]} {
set all_tri_nets ""
}
}
set num_pins [sizeof_collection $all_tri_pins]
echo "there are $num_pins pins to process"
while {[sizeof_collection $all_tri_pins] != 0} {
set mypin [index_collection $all_tri_pins 0]
set tri_net [all_connected $mypin]
set net_name [get_attribute $tri_net full_name]
echo "processing net $net_name for a set_bounds"
set bound_pins [all_fanin -flat -levels 0 -to [get_net $tri_net]]
set bound_pins [add_to_collection -unique $bound_pins \
[all_fanout -flat -levels 0 -from [get_net $tri_net]]]
set all_tri_pins [remove_from_collection $all_tri_pins $bound_pins]
set bound_cells [get_cell dummy]
foreach_in_collection target_pin $bound_pins {
set pin_name [get_attribute $target_pin full_name]
if {[regexp {(.*)/[^/]+$} $pin_name match cell_name] != 0} {
set bound_cells [add_to_collection -unique $bound_cells \
[get_cell $cell_name]]
}
};# end of foreach loop for target bound cells
set_bounds -effort high $bound_cells
set count [sizeof_collection $all_tri_pins]
echo "there are $count pins left to process"
# check for the existance of the go flag to continue procedure
if {![file exists .go]} {
set all_tri_pins ""
}
};# end of while loop for tri state pins
echo "Completed - procedure tri_state [date]"
# remove the go flag
file delete .go
unset all_tri_nets
unset all_tri_pins
};# end of procedure
============================================================================
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\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
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