( ESNUG 381 Item 4 ) -------------------------------------------- [11/08/01]
Subject: ( ESNUG 380 #1 ) Conflicting Stories On Mosys RAM Soft Error Issue
> b) MoSys hasn't addressed the soft-error issue, so make sure you leave
> plenty of room for (non-MoSys) RAMs for parity and ECC (especially
> if your application is byte-wide). (It's a shame MoSys didn't
> adjust their form-factors for this).
>
> - [ Captin Krunch ]
From: [ "Kitty", from Monsters, Inc. ]
John,
Funny he should mention that. I was just talking to a MoSys field guy,
and he recommends ECC, for exactly that reason. I'm not sure that the guy
would want me to talk about _exactly_ what he said, since he indicated that
the product had considerably worse than expected performance versus alpha
particles. Please make me anon if you print this.
What I was told was that the performance versus soft errors was so bad as
to make the devices useless for their nominal purpose. When I suggested
that parity connected to a reset circuit would be good enough for most
applications, he grunted and said that you really want to use ECC. I didn't
ask for details, like error/second numbers, but the implication was pretty
clear.
I am _not_ an expert on MoSys's technology, just have bumped into it a few
times. The word on the street is that MoSys uses an unusual, low-transistor
design, which allows them to get a lot more bits onto a given chip. The
word is also that there are more problems with soft errors, which figures.
- [ "Kitty", from Monsters, Inc. ]
---- ---- ---- ---- ---- ---- ----
From: "Mark-Eric Jones" <mejones@mosys.com>
Hi John,
I was surprised in your last ESNUG to see a letter from someone [ Captin
Krunch ] who said that MoSys isn't addressing the SER issue. MoSys is
VERY aware of the soft error issue, and takes a stand that our 1T SRAM has
great SER characteristics! As a matter of fact, I gave a paper at Design
Con 2001 regarding this very issue. Could you please put it in your
DeepChip.com download section so users can read it? Here is an excerpt
from our Design Con paper:
"So what are the reasons for the very good SER characteristics of
1T-SRAM technology compared to traditional SRAM? Firstly, the
relatively high capacitance in the bit cell helps ensure a high
critical charge is required to upset the cell. In addition, the fact
that MoSys' architecture divides the memory into a very large number
of small banks (typically many hundreds of banks in a normal macro)
results in a memory with very short bit lines for sensing the memory
cell contents. This results in large internal margins during
sensing combined with less bit line charge collection area. Also
the exclusive use of p-channel structures in the memory core array,
protected by an n-well helps improve the SER characteristics of
1T-SRAM memory."
Also, in an article that Anthony Cataldo wrote on "SRAM soft errors cause
hard network problems" I stated "the failure in time (FIT) of MoSys' 1T
SRAM is below 1,000 and will stay that way down to 0.13 um, while SRAMs
are on track to hitting 10,000 FITs at 0.15 um. Here's the link:
http://www.eetimes.com/story/OEG20010817S0073
MoSys does take the soft error issue seriously and our 1T SRAM has good SER
characteristics.
- Mark-Eric Jones, VP
MoSys Sunnyvale, CA
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