( ESNUG 381 Item 9 ) -------------------------------------------- [11/08/01]
From: "Mike Montana" <montana@synopsys.com>
Subject: PhysOpt Tcl Script To Simplify Stitching Together Top Level Blocks
Hi, John,
One problem my PhysOpt customers sometimes face is getting the top level
ports in their logical netlist to align with the top level pads in their
physical design. PhysOpt makes this association automatically if the
cells in the logical library have the proper attributes. That is:
1. Each I/O pad cell has the "pad_cell" attribute
2. The physical pad on each I/O cell has the "is_pad" attribute
Unfortunately, some libraries do not contain these attributes. In this
case, the PhysOpt commands will not run and the user will sees:
Error: Cannot inherit location from pad pin 'reddog_iox/io9/IOBUFx/N01'
to port 'AD09X' because this cell reddog_iox/io9/IOBUFx is not a
real pad cell. Please check the library. (PSYN-117)
Error: Port AD09X has no location. (PSYN-007)
When these errors occur, the user has a couple of options. Contact the lib
vendor and ask them to add the proper attributes to their libraries. (Great
long term solution but not necessarily the fastest!) Or the user can
identify the I/O cells and modify the library to have the proper attributes.
Again, a great solution but what happens if you do not have an ASCII version
of the vendors library?
An AC up in Denver came up with a very fast and efficient way to solve this
problem. He wrote a tcl script which parses a log file from a PhysOpt run
to identify I/O cells missing these key attributes. The script's output can
be sourced into PhysOpt and it will then apply all of the necessary
attributes to the libraries. Here is how the flow works:
1) Load the design and PDEF into PhysOpt. Run physopt -check_only and be
sure to redirect the result to a log file i.e.
psyn_shell> physopt -check_only > check_only.log
2) Examine the log file and see if there are any problems related to top
level port locations ( i.e. PSYN-117 or PSYN-107). If so, run the tcl
script provided in a UNIX shell environment.
UNIX> is_pad.tcl check_only.log fixio.tcl
3) Source the resulting fixio.tcl script in your current psyn_shell
session and your top level ports will now automatically be located by
PhysOpt based on the top level I/O cells. Here is a sample fixio.tcl
script:
set top_name [current_design]
current_design [ get_attribute [ find cell bigchip_iox ] ref_name ]
current_design [ get_attribute [ find cell io0 ] ref_name ]
set_attribute -type boolean [get_lib_cells \
-of_objects [find cell IO1Cx ] ] pad_cell true
current_design $top_name
set_attribute -type boolean [find pin \
bigchip_iox/io0/IO1Cx/N01 ] is_pad true
set top_name [current_design]
current_design [ get_attribute [ find cell bigchip_iox ] ref_name ]
current_design [ get_attribute [ find cell io1 ] ref_name ]
set_attribute -type boolean [get_lib_cells \
-of_objects [find cell IO1Cx ] ] pad_cell true
current_design $top_name
set_attribute -type boolean [find pin \
bigchip_iox/io0/IO1Cx/N01 ] is_pad true
Two things to remember:
1) You will need to modify the first line of the script to point to your
tcl-tk install path.
2) Once you create the fixio.tcl script, you will need to source it each
time you start a PhysOpt session. The script applies the proper
attributes to the library loaded in memory. It does NOT modify the
library.db file provided by the vendor.
The script has been tested using PhysOpt 2000.11 and 2001.08.
- Mike Montana
Synopsys, Inc. Dallas, TX
#!/depot/tk-8.1/bin/wish8.1
# Script name: is_pad.tcl
#
# Input: Transcript/logfile of a Physical Compiler run that
# encounters the PSYN-117 error.
# Output: A script that you can source in your synthesis
# script. Be sure to source this generated script
# after you have read in the design and linked it
# (the key is to make sure the libraries exists in
# memory).
# Disclaimer: Scripts have been tested for Physical Compiler
# versions 2000.11 and 2001.08
#
# Example Execution:
# is_pad.tcl check_only.log fixio.tcl
#
puts "is_pad.tcl processing beginning..."
set debug 0
set verbose 1
set i 0
foreach arg $argv {
incr i
if {$debug == 1 } {
puts "arg = $arg"
}
if {$i == 1} {
set inputfile $arg
}
if {$i == 2} {
set outputfile $arg
}
}
if {$debug == 1 } {
puts " inputfile is $inputfile"
puts " outputfile is $outputfile"
}
if [catch {open $inputfile r} inputID] {
puts "cannot open file '$inputfile'" ; exit
}
if [catch {open $outputfile w} outputID] {
puts "cannot open output '$outputfile' file for writing." ; exit
}
while { [gets $inputID line] >= 0 } {
if {$debug == 1 } {
puts $line
}
# remove tabs, replace with single space
regsub -all \t+ $line { } line
# remove beginning spaces from line
regsub -all {^[ ]+} $line {} line
set pad_pin_name ""
set pad_name ""
set Keyword ""
# if first word on the line is Error: then parse the line.
scan $line "%s" Keyword
if {$Keyword == "Error:"} {
# Parse the current line
# look for the error code of PSYN-117 in the line
set value [ string first "(PSYN-117)" $line ]
if { $value != -1 } {
# if found the error code, then parse out the name of the pad pin.
# Note $position_of_pad_pin_name is the length of the error
# string to the first ' in the following line:
# Error: Can not inherit location from pad pin '
set postion_of_pad_pin_name [expr [string first "'" $line] + 1 ]
# find the position of the last character in the pad name
set len [string length $line]
set new_string [string range $line $postion_of_pad_pin_name $len]
set i [expr [string first "'" $new_string ] - 1]
#strip out the pad name from the line
set pad_pin_name [string range $new_string 0 $i]
if {$debug == 1 } {
puts $pad_pin_name
}
# find the position of the last character in the pad name
set i [expr [string first "cell" $line ] + 5]
set new_string [string range $line $i $len]
set i [expr [string first " " $new_string ] - 1]
#strip out the pad name from the line
set pad_name [string range $new_string 0 $i]
if {$debug == 1 } {
puts $pad_name
}
}
}
# set the appropriate attribute
if { $pad_name != ""} {
# now need to traverse the hierarchy to the leaf cell
# if find hierarchy then set the current design to the leaf cell
puts $outputID "set top_name \[current_design\]"
set i [expr [string first "/" $pad_name ] - 1]
while { $i > 0 } {
set name [string range $pad_name 0 $i]
puts $outputID "current_design \[ get_attribute \
\[ find cell $name \] ref_name \]"
set i [expr $i + 2]
set len [string length $pad_name]
set pad_name [string range $pad_name $i $len]
set i [expr [string first "/" $pad_name ] - 1]
}
puts $outputID "set_attribute -type boolean \
\[get_lib_cells -of_objects \[find cell \
$pad_name \] \] pad_cell true"
puts $outputID "current_design \$top_name"
}
# if found pad pin name, then output to tcl script to
# set the appropriate attribute
if { $pad_pin_name != ""} {
puts $outputID "set_attribute -type boolean \[find pin \
$pad_pin_name \] is_pad true"
}
}
puts " Completed parsing $inputfile"
close $inputID
close $outputID
exit
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