( ESNUG 383 Item 6 ) -------------------------------------------- [11/28/01]
Subject: ( ESNUG 382 #8 ) Negative Timing Checks Is A *Cadence* Problem
> This Verilog-XL "bug" shows up when back-annotating an SDF file with
> negative hold times and using the +neg_tchk option. Verilog should use
> the negative hold times correctly, but instead will set the negative
> values to zero without issuing an error or warning.
>
> - Stefan Griebel
> Cirrus Logic
From: "Rakesh Kinger" <rkinger@broadcom.com>
Hi, John,
This is a Cadence issue, not a Verilog issue. Synopsys VCS handles each edge
independently, so negative limits won't be rounded to 0 and each edge has its
own independent violation window. This is how VCS preserves the sanctity of
its negative timing checks and simulates according to user intention.
This capability is enabled via "+overlap" VCS compile-time flag. You also
need to use "+neg_tchk" and "+multisource_int_delays" assuming you're using
VCS 6.1 Beta2 like I am.
Let me explain this in detail.
The example Stefan Griebel gave has two timing checks on the same data signal
w.r.t. posedge clock and the violation regions of the competing timing checks
are non-overlapping.
e.g. $setuphold(posedge CK, posedge D, 4, -3);
$setuphold(posedge CK, negedge D, 2, -1);
Stefan says NC-Verilog and Verilog-XL are unable to handle these timing checks
and they erroneously reduce them to zero.
e.g. $setuphold(posedge CK, posedge D, 4, 0);
$setuphold(posedge CK, negedge D, 2, 0);
As a result if there is a change at D 0.5 timeunits *before* the clock these
simulators will give a setuphold violation. This is incorrect and not we want.
VCS will mantain the (4,-3) violation window for posedge D and the (2,-1)
violation window for negedge D. If D changes 0.5 units *before* the clock,
since doesn't zero out anything, you won't get any timing violation (i.e.
VCS behaves correctly here.)
And, BTW, Verilog libraries should also support negative timing checks using
extended syntax of $setuphold checks as shown below :
$setuphold(posedge phi,posedge d,0,0,notify_reg,,,delay_phi,delay_d);
$setuphold(posedge phi,negedge d,0,0,notify_reg,,,delay_phi,delay_d);
where delay_phi and delay_d are declared as wires.
- Rakesh Kinger
Broadcom Corporation San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: Keith Howick <howick@siliconmetrics.com>
John,
I have run into this in Verilog-XL before while working on a characterization
flow for one of our customers. This was about two years ago and at that time
our characterization tool only captured setup and hold in an independent
fashion. When captured this way it's pretty common to get non-overlapping
violation regions. The problem caused our customer so much grief that they
decided to live with lost performance and asked us to build a script to
post-process our characterization results to guarantee an overlap.
The problem disappears when sequential cells are properly characterized.
During our research into this problem we rediscovered an age-old truth: setup
and hold aren't independent measurements. Properly characterized setup and
hold is the minimum pulse-width for a synchronous pin (e.g., data). Setup
and hold were created to accomodate the dependency of synchronous MPW on its
location relative to the clock.
My evidence is purely empirical, but when setup and hold are captured
correctly in a totally dependent manner (which we do today) the violation
regions always overlap.
- Keith Howick
Silicon Metrics Corp.
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