( ESNUG 385 Item 1 ) --------------------------------------------- [12/19/01]
From: Jenny Yee <jyee@synopsys.com>
Subject: DC Creates Incorrect Logic With Verilog Signed/Unsigned Arithmetic
Hi, John,
Design Compiler 2001.08 might generate incorrect logic (STAR-131010) when
all of the following conditions are true:
* Verilog code uses signed and unsigned arithmetic (Verilog 2001)
* Different bit-widths are used
* Tree-height minimization is invoked by Design Compiler
The following design will be incorrectly compiled if tree-height minimization
is invoked:
module bad (a, b, c, z);
input [4:0] a, b;
input signed [4:0] c;
output [6:0] z;
wire signed [5:0] tmp_1;
assign tmp_1 = a + b; // unsigned
assign z = tmp_1 + c; // signed
endmodule
You can work around this problem by using the following two methods.
1. Disable tree-height minimization by:
hlo_minimize_tree_delay = false
Tree-height minimization is invoked based on optimization requirements.
In the above example, it will be used if input "a" arrives late.
2. Modify your Verilog code. Here's an appropriate modification:
module ok (a, b, c, z);
input [4:0] a, b;
input signed [4:0] c;
output [6:0] z;
wire signed [6:0] tmp_1, tmp_c;
// unsigned operation -> convert to signed
assign tmp_1 = {2'b00, a} - {2'b00, b};
assign tmp_c = {c[4],c[4],c}; // extend sign
assign z = tmp_1 + tmp_c; // signed
endmodule
A software fix will be available in January 2002 and will be available to
all users in the general Synopsys' 2001.08-SP2 Service Pack release.
Again, if you are not using the Verilog 2001 signed/unsigned features, this
won't be an issue for you.
- Jenny Yee
Synopsys, Inc. Mountain View, CA
|
|
