( ESNUG 385 Item 8 ) --------------------------------------------- [12/19/01]
Subject: ( ESNUG 383 #2 ) We Can't Duplicate The Alleged PhysOpt "Case" Bug
> My design has signal names with UPPER and lower case. When I'm doing
> 'write_script' in PhysOpt, it writes all of the signals in lower case.
> Verilog doesn't like this. How can I fix PhysOpt so the names in the
> write_script will be liked in Verilog?
>
> - Ofer Paperni
> Motorola
From: "Mike Montana" <montana@synopsys.com>
Hi, John,
I saw Ofer's post to ESNUG and was a little perplexed. I have several
customer designs with a mixture of upper and lower case names and I find
that the write_script command in Physical Compiler outputs the net names
without any changes. Can he provide a little more detail about his
situation? Is Ofer running any change_names commands as part of his flow?
Perhaps with a few more details, I can help out.
- Mike Montana
Synopsys, Inc. Dallas, TX
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