( ESNUG 388 Item 10 ) -------------------------------------------- [02/27/02]
Subject: ( ESNUG 387 #8 ) Remove That Extra Hierarchy Power Compiler Creates
> We're using clock gating and scan insertion in DC with a custom clock
> gating cell. I've specified the clock_gating_style as a sequential
> latch with control_point set to before and some appropriate bitwith and
> max_fanout settings. Works fine through synthesis, but the output result
> from DC adds a boatload of unique SNPS_CLOCK_GATE* wrappers around the
> clock gating cell for all instances where the clock gating cell would
> be added:
>
> module SNPS_CLOCK_GATE_HIGH_hdwb_0 ( CLK, EN, ENCLK, TE );
> input CLK, EN, TE;
> output ENCLK;
> GCKAD4 latch ( .TE(TE), .EN(EN), .CLK(CLK), .ENCLK(ENCLK) );
> endmodule
>
> Power Compiler adds this hierarchy at elaboration to attach a batch of
> attributes required to map the clock gating cells, presumably for clock
> gating and scan insertion. However, when going through the layout flow,
> all of these modules represent an extra layer of hierarchy that needs to
> get processed. Is there a way eliminate this extra layer of hierarchy and
> still preserve the clock gating and scan attributes? It seems to me that
> DC should just instance the cell and attach the attributes to the
> instance.
>
> Removing this layer of hierarchy would really cut down the amount of
> instances that need to get processed further down the layout methodology
> path.
>
> - Gregg Lahti
> Corrent Corp. Tempe, AZ
From: "Hamid Nassiri" <hamidn@synopsys.com>
Hi, John,
Clock-gating cells created by Power Compiler have their own hierarchy.
The wrapper design SNPS_CLOCK_GATE* contains the gating elements. It
also preserves the clock-gating attributes. These attributes are needed
for the remove_clock_gating, rewire_clock_gating, and report_clock_gating
commands to work properly. When the SNPS clock-gating cells are ungrouped,
the clock-gating information is lost due to the loss of these attributes.
In the 2001.08 release Power Compiler introduced the power_cg_flatten
variable. By default, it preserves SNPS clock-gating cell hierarchies
during ungroup. This allows the commands mentioned earlier to work fine
because the clock-gating attributes are kept. The default setting for
this variable is "false". When set to "true", it allows the ungroup
command to flatten these cell hierarchies. But then, the clock-gating
attributes are lost and the commands related to clock gating mentioned
before will not work properly. The above description holds true for
"integrated" clock-gating cells as well.
Please note this feature has been documented in the 2001.08 Release Note.
- Hamid Nassiri
Synopsys, Inc. Sunnyvale, CA
---- ---- ---- ---- ---- ---- ----
From: "Gregg Lahti" <gregg.lahti@corrent.com>
Hi, John,
I got it figured out after a few email exchanges from the SNPS AE Chris
Papademetrious -- a big thanks to Chris for his invaluable input. SNPS
added a feature in the Power Compiler section of 2001.08 that enables
smashing of the extra hierarchy:
set power_cg_flatten true;
However, you must set this flag and then run an ungroup to completely
remove the extra hierarchy. I've got two methods to do the ungroup:
1) Compile as normal and run the following Tcl procedure to break up the
hierarchy:
# Usage: P_proj_ungroup_cg
#
# This procedure is used to ungroup the clock gating components
# (SNPS_CLOCK_GATE_*) extraneous hierarchy. Useful so that layout
# doesn't need to deal with thousands of 1-cell hierarchy designs.
proc P_proj_ungroup_cg {} {
echo "#UNGROUP_CG: ungrouping clock gating hierarchy"
# Save current location
set this_design [get_object_name [current_design]];
# Need to traverse through hierarchy & flatten CG components
redirect $sh_dev_null {set hier_designs [filter [find design *] \
{@is_hierarchical == true}]};
if {$hier_designs != {}} {
foreach_in_collection tmp_design $hier_designs {
redirect $sh_dev_null {set current_design $tmp_design};
redirect $sh_dev_null {set cell_list [filter [find cell *] \
{@pwr_cg_design_is_clock_gating == true}]};
if {$cell_list != {}} {
foreach_in_collection tmp_cell $cell_list {
echo "#UNGROUP_CG: ungrouping" [get_object_name $tmp_cell] \
"in design" [get_object_name $tmp_design];
ungroup $tmp_cell -flatten -prefix CG_ -simple_names;
}; # end foreach_in_collection
}; # end if
unset cell_list;
}; # end foreach_in_collection
unset tmp_design;
}; # end if
# Reset current back to where we started from */
redirect $sh_dev_null {set current_design $this_design}
# Clean up namespace
unset this_design
unset hier_designs
}; # end P_proj_ungroup_cg
define_proc_attributes P_proj_ungroup_cg \
-info "PROJ_PROCS: Used to ungroup the SNPS_CLOCK_GATE_* clock gating
hierarchy for the design"
2) Or, set the following variable after elaboration of the design but before
the compile command:
set_ungroup [get_designs {SNPS_CLOCK_GATE_*}];
This was suggested by Chris initially, but didn't work without setting
the power_cg_flatten to be true. This command ungroups designs during
the compile (after the initial mapping but before optimization) to
ungroup the appropriate designs. A much easier command and a lot less
Tcl code.
A side note -- I tried the set_ungroup command frome example (2) to remove
extraneous DesignWare hierarchy but it didn't work. I use essentially the
same script from example (1) (replace the @pwr_cg_design_is_clock_gating
with @DesignWare, replace CG_ with DW_) to smash the DW hierarchy into plain
standard cells after the compile phase.
- Gregg Lahti
Corrent Corp. Tempe, AZ
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