( ESNUG 389 Item 11 ) -------------------------------------------- [03/06/02]

From: Mouli Gopalakrishnan <cgopalak@csee.usf.edu>
Subject: Can't Get Static Leakage Power Of A NAND Gate In NanoSim/PowerMill

Hi John,

I have a question regarding measurement of static leakage power using
NanoSim (formerly EPIC's PowerMill tool.)  I wasn't satisfied with the
Synopsys tech support's answer.  :(

What I am trying to measure is the static wasted power in a NAND gate (or
for that matter any circuit ... I am starting off small).  Input is a HSPICE
netlist of a NAND gate (4 transistors).  Inputs to the NAND gate are 2 dc
inputs.  Simulation time for some 400 nsec (arbitrary).  What I want is the
leakage power dissipated due to the subthreshold leakage currents flowing
through the dc paths.

I do this using HSPICE by printing out VGS values and determining if each
transistor is ON/OFF and measuring the instantaneous power at that time if
it is OFF.  This is time consuming and tedious and I wish there is a way by
which a tool like NanoSim could help me.  :(

I was reading in the documentation NanoSim does measure leakage (wasted)
current -- both static and dynamic.  I have been trying to use the
track_wasted and split_wasted option.  According to the docs, it says
the split_wasted option splits the wasted currents (powers) into
static and dynamic.  I tried it out for a simple nand gate.  My input is
in the form of a SPICE netlist:

    .inc 'TSMC-0.35um.model'
    .global GND

    V_vdd Vdd GND 1V

    *V_a A1 GND PWL (0n 0 49n 0 50n 1 100n 1 101n 0)
    *V_b B1 GND PWL (0n 0 100n 0 101n 1)

    V_a A1 GND dc 0.0
    V_b B1 GND dc 1.0


    * HSPICE file created from nanf201.ext - technology: SCN4M.25.TSMC

    .option scale=0.25u

    m0 O A1 Vdd Vdd CMOSPL w=25 l=2
    + ad=150 pd=62 as=242 ps=132 
    m1 Vdd B1 O Vdd CMOSPL w=25 l=2
    + ad=0 pd=0 as=0 ps=0 
    m2 a_13_3 A1 GND GND CMOSNL w=21 l=2
    + ad=42 pd=46 as=105 ps=52 
    m3 O B1 a_13_3 GND CMOSNL w=21 l=2
    + ad=79 pd=52 as=0 ps=0 
    C0 Vdd GND 6.8fF

    ** hspice subcircuit dictionary

    **.measure tran Vdd_pwr avg power from=0ns to=400ns

    .tran .1ns 200n
    .end

My cfg file:

    report_block_powr total track_power=1  split_wasted=1 *


When I ran the above circuit, it gives dynamic wasted = 0 W and static
wasted = 0 W and % Wasted power = 100%.  I understand the dynamic wasted
part -- since there is no switching activity, there cant be short circuit
currents -- but shouldn't there be some static leakage power ??

Can someone point out to me, what I am doing wrong -- or is the simulator
not capable of getting this value ??   I would really appreciate if someone
sheds some light on this for me.

    - Mouli Gopalakrishnan
      University of South Florida                Tampa, FLA


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