( ESNUG 392 Item 1 ) --------------------------------------------- [04/18/02]
Subject: Synopsys R&D Q&A To The SNUG'02 Design Compiler Tutorial (Day 1)
1. You mentioned that ILM keeps only the interface logic. What do you
mean by "maintaining logical hierarchy"?
Some designs have combinational logic through several levels of
hierarchy before it reaches a register, Design Compiler ILM is able
to extract all of that.
2. Can you view ILMs in Design Vision and Design Analyzer?
Yes. ILMs are treated as any other regular netlists in Design Vision
and Design Analyzer.
3. How are latches handled in ILM? Does it support time borrowing?
Latches are handled as combinational logic by default. However, you
can control it and specify the levels of latches allowed for time
borrowing. This is discussed in more detail below.
4. If you have a synchronous reset in your design that fans out to many
flip-flops, how does ILM accurately account for this if you use
ignore_port on it?
The fanout information is preserved when you set the -include_side_load
option to boundary (default) or all.
5. Why would you use a top-level compile with ILMs if your reset fanout is
removed? In this case, the reset net is not going to be buffered up,
correct?
The reset fanout is preserved unless you choose not to include the
side_loads.
In this case, the reset net is not going to be buffered up.
6. Does ILM's boundary logic get optimized during compile?
No, this is a future enhancement that we are working on.
7. Is the side load the lumped load or the actual load of the cell?
The side load is the actual load of the cell, not the lumped load.
8. Is transition time of the nets preserved for ILM?
No, transition time is not preserved. It is recalculated during
timing analysis.
9. If I perform scan insertion in the top level, can I do DRC fixing
with ILM?
Yes. DRC fixing and scan insertion work independently of each other.
10. Will clock-gating information and structures inserted by Power
Compiler be preserved in ILM?
They will be if they are part of the interface logic.
11. What about handling for clock tree delays in the ILM models after
layout?
Not currently available. These are possible future enhancements,
which we are looking into.
12. Does Design Compiler pull a HDL Compiler license when it reads in a
structural netlist with the Verilog netlist reader?
No HDL Compiler license is required to read a gate-level netlist with
the explicit -netlist option. However, if the netlist reader is used
via the new scanner, a HDL Compiler license will be pulled.
13. Does Design Compiler require that you recompile the vender libraries
with the added "when" constructs?
In most cases, no. Most vendors already have this information in
their libraries (for PrimeTime). Design Compiler was just not using
it in the previous releases.
14. Are you forced to use case analysis for conditional arcs?
Not necessarily. Logic constants will work, too. The baseline is
that a conditional arc does not make any sense if the input pins are
not constants.
15. Are conditional arcs accounted for during the optimization phase or
only during timing analysis?
Conditional arcs are also accounted for in the optimization phase.
16. For the new bidirectional enhancements, does it mean that designers
have to determine those paths are actually false paths?
Yes, designers need to make sure those are indeed unwanted paths in
their designs.
17. Does Design Compiler also disable the timing arcs through Enb to FF2
(slide 44 in the tutorial)?
Yes. Both loop-through timing paths to FF2 are disabled.
18. Where does ideal_network stop?
It stops at registers or cells that have non-ideal or non-constant
inputs.
19. What is the difference between don't_touch_network and
ideal_network?
Dont_touch_network still has actual delay and transition, whereas
ideal_network by default has zero delay and transition.
20. What is the difference between auto_disable_drc_net and ideal_net?
Auto_disable_drc_net disables drc fixing, whereas ideal_net disables
both DRC and timing fixing.
21. Does ideal_network apply only to input ports? What happens when you
apply it to output ports?
Applying ideal_network to output ports is not useful because the
command helps timing and optimization of logic within the design.
However, you can apply ideal_network to hierarchical output pins
driving other subblocks.
22. Is transition time calculated in ideal_network?
Ideal_network assumes ideal_transition and defaults to zero, but you
can change the value.
23. Should U4 be a boundary cell (slide 54 in the tutorial)?
No, because both of the inputs are ideal.
24. Can high_fanout_net_threshold be set on individual nets?
No. High_fanout_net_threshold applies to your current design, not on
a per-net basis.
25. Do extracted timing models (ETMs) extract timing arcs only? How would
ETMs apply to internal pins?
Yes, ETMs have timing arcs. However, it is possible to have timing
arcs to and from internal pins in ETMs.
26. Does PrimeTime use the trip points only from the very first library
in the link path or does it search for the first library that has trip
points?
Version 2001.08 of PrimeTime uses the trip points only from the first
library specified in the link path. However, version 2002.03 of
PrimeTime has multithreshold values from different libraries by
default.
If you want to go back to the previous behavior (version 2001.08),
you can set the following variable to false:
set lib_thresholds_per_lib false
The default setup of this variable is true.
27. Is the new sequential mapping similar to set_prefer?
No. Using set_prefer is a manual way of setting the preferred
lib_cells in the library so that so that the sequential mapper can
choose those cells first. It still does not guarantee that the
mapper uses the sequential cells correctly.
For example, it might use D-FF with sync_reset, but it might hook up
constant to reset input of the cell (and AND gate to D input of the
FF). The new sequential mapper can recognize complex registers.
28. What registers do you get if you leave out the Synopsys compiler
directive in your example slide 69 in the tutorial)?
It depends. It is not the function of the sequential mapper. Rather,
it is the function of HDLC, which might pick out a correct sequential
element. But in many cases, it generates unexpected results. For
example, it ties D signal to sync_reset input and combinational
circuit to D input. It's functionally is correct, but it may not be
what you expected.
On the complex sync registers (set_FF, reset_FF, set_reset_FF,
load_set_reset_FF, and so on), all of the sync inputs are considered
similar (except for timing). Unless HDL Compiler recognizes which
signals are for which, you might get unexpected results.
29. Are all the new optimizations/commands you have mentioned also
supported in Physical Compiler?
Most of new optimization features and commands are supported in
Physical Compiler. However, some are specific to logic synthesis
only and are not applicable to the physical spectrum. Some commands
do have options for Physical Compiler only, for example,
extrac_ilm -physical.
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