( ESNUG 392 Item 6 ) --------------------------------------------- [04/18/02]
Subject: Synopsys R&D Q&A To The SNUG'02 ACS Tutorial (Day 2)
51. Does a top-down compile invoke budgeting "under-the-hood"?
No. In a top-down compile, Design Compiler views all hierarchical
designs and interconnects at one time. This process is the same
as compiling a single module except that Design Compiler must
respect the interconnects across design hierarchy. Therefore, only
the constraints (or budget) assigned to the top level are used.
Lower-level budgets are ignored.
52. Does acs_recompile_design go back to RTL for optimization?
The acs_recompile_design command uses the pass0/precompile .db files
by default for optimization. In a usual Automated Chip Synthesis
flow, pass0/precompile .db files are the elaborated GTECH .db files.
However, for budgeting purposes, the acs_recompile_design command
uses the pass0/postcompile .db files by default. This enables the
acs_recompile_design command to create better budgets, but by using
the elaborated .db files, have a better starting point for
optimization.
The acs_recompile_design command has switches (-budget_source and
-source) that allow you to separately specify what pass the .db files
should come from for budgeting and for optimization. Therefore you
use another .db file besides the elaborated .db as an input to
acs_recompile_design.
53. What is acs_merge_design?
The acs_merge_design command must be used when you use the default
Automated Chip Synthesis directory structure for incremental design
updates. Using pass0 as an example, a regular acs_compile_design
will use the .db files in elab/db as input and produce output .db
files in pass0/post_compile.
The first time acs_compile_design -update is used, it will copy the
.db files not changing from pass0/postcompile to pass0_incr/precompile
and copy the .db files to be updated from elab/db to
pass-incr/precompile. New results will be stored in
pass0_incr/postcompile.
From this point on, each time acs_compile_design -update is used,
acs_merge_design must be used to combine the latest changes from the
pass0_incr/postcompile directory with the new elaborated .db files and
create a valid pass_incr/precompile .db. If acs_merge_design is not
used, previous design updates could be lost and your postcompile .db
will become out of sync with your RTL.
To avoid the need to use acs_merge_design and to simplify the directory
structure, you can simply not use the pass0_incr directory. Just
redirect acs_compile_design -update to use the pass0 directory for
input and output using the -update_source and -destination switches.
54. What is the recommended design size for Automated Chip Synthesis at
the top level?
There is no specific recommendation. Most users of Automated Chip
Synthesis find that partitions of 50K to 150K gates are reasonable.
Ideal size varies significantly with design style, workstation
configuration, design constraints, and so on. If you are trying to
take advantage of parallel synthesis of multiple partitions, then
ideally you should keep the load balanced between partitions.
Larger partitions result in better the QOR but longer runtimes.
55. Does Automated Chip Synthesis have the ability to check out a
license needed beforehand or must it wait for the required license?
The Automated Chip Synthesis variable acs_lic_wait allows you to
specify the number of minutes to wait for a license before quitting.
For more information about the use of this variable, see the
acs_variables man page.
56. What is the percentage of customers that have adopted Automated Chip
Synthesis?
We know of several customers that are successfully using Automated
Chip Synthesis in their standard production flow. Because Automated
Chip Synthesis is not a separate feature license, we do not have
detailed usage information.
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