( ESNUG 394 Item 13 ) -------------------------------------------- [05/29/02]
Subject: ( SNUG 02 #7 ) It's Obvious SystemC Failed; Superlog Is The Future
> "I think that it's plain old Verilog up in front, with Superlog a length
> behind, and SystemC asleep at the starting gate."
>
> - Dave Chapman of Gold Mountain
From: Nick Skelton <nick.skelton@freehand.se>
Hi John,
I just read your SNUG trip report report. I had been thinking that you kept
mis-filing Superlog by lumping it into threads about SystemC. Surely
everyone has now seen that design in C is not going to fly. And you
shouldn't have been listing Superlog with the languages like E and Vera.
Maybe you were right after all. E and Vera are so entrenched in that space,
even if Superlog has all their verification features, and is easier to use,
it will still take ages to dislodge them.
In design and especially sub block verification however Superlog is good.
The subblock designers, who really want have have access to all the
verification features, don't want to have to learn a new weird language.
We at Freehand have been using the SystemSim Superlog simulator for 3 years
now. We like it. It's robust and fast. Superlog can't do VHDL, but it
does simulate C together with Verilog rather well. We use that a lot.
- Nick Skelton
Freehand DSP AB Sweden
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